This class I took during my fall 2000 semester. It deals with VHDL language and the programming creation of parts and simulation.
The file pkmips.vhd was used, updated, and provided by the instructor.
Original (org.) files are the original files given by the instructor, and the New files are those changed and/or corrected.
The first lab was mainly instructional. We were to modify an AND file from its original sequence to a new one. To test it a test bench (tb) file was used. The test bench was also modified so that a new sequence was run to test the file. The final test of the lab can be seen here. Files used: and2.vhd, tband2.vhd (org.), tband2.vhd (new).
This lab is to fix the code so that extends the sign bit of half size data word into full size data word output. The incorrect simulation is here and the correct simulation is here. Files used: sgnext.vhd (org.), sgnext.vhd (new), tbsgnext.vhd.
This lab has two parts to it. The first part was to correct a file so that it counts how many bits are displayed. The incorrect simulation is here and the correct simulation is here. File used: cnt1s.vhd (org.), cnt1s.vhd (new), tbcnt1s.vhd.
The second part was to fix a PC register so that it functions correctly. The incorrect simulation is here and the correct simulation of it is here. The PC loads a value and increments it by four evey time it loads the number. The files used are here: pc.vhd (org.), pc.vhd (new), tbpc.vhd.
This lab is to fix a Mod 10 binary counter. The incorrect simulation is here and the correct simulation is here. Files used: swclk.vhd, cntmod10.vhd (org.), cntmod10.vhd (new), tbmod10.vhd.
Lab 5 is the first big project yet. We were to take and finish the code for an ALU design and test it. The simulation is here, and zoomed in version for 200 ns intervals are here: 0-200 ns, 200-400 ns, 400-600 ns, 600-800 ns, 800-1000 ns. Files used: alu.vhd (org.), alu.vhd (new), tbalu.vhd (org.), tbalu.vhd (new).
This lab was to construct a complete ALU using the ALU slices developed in the alu.vhd file from lab 5. The full simulation is in 2 parts: Part 1, Part 2. Zoomed in views of each function are here: 0-320 ns, 320-640 ns, 640-960 ns, 960-1280 ns, 1280-1600 ns. Files used: bigalu.vhd (org.), bigalu.vhd (new), tbbigalu.vhd.
The final lab is the creation of a finite state machine. When a value is loaded into the machine it reads and determines what function is to be done and dislplays the sequence that it should be. The full simulation is here. A zoomed view of the sections are here: Reset, ADD, SUB, slt, OR, AND, lw, sw, beg, j. Files used: cufsm.vhd, tbcufsm.vhd.
