----------------------------------------------------------------------
-- File:     cufsm.vhd - KIPS Control Uniits Finite State Machine
-- Author:   
-- Creation: 
-- Verified: ...                 
-- Version:  
-----------------------------------------------------------------------
--Requires: pkgmips.vhd Version 2.0
LIBRARY IEEE;
USE work.mips.all;
USE IEEE.Std_Logic_1164.all; 
USE IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
------------------------------------------------------------------------
-- FUNCTION: cufsm  - Finite state machinne for Kips control unit as 
--                    described in sectioon 5.4 of of Hennessy and 
--                    Patterson.
--   INPUTS: CLK    - Clock falling edge  causes state transiton.
--           RES    - Reset signal Puts FFSM in S0
--           IR     - Instruction Registeer
--  OUTPUTS: S      - State of FSM
------------------------------------------------------------------------
ENTITY CUFSM IS
     PORT(CLK:          IN std_logic;
          RES:          IN std_logic;
          IR:           IN std_logic_vector(CWordSize-1 downto 0);
          S:            OUT STATE
         );
END ENTITY CUFSM;

ARCHITECTURE behav OF CUFSM IS
BEGIN
    GetNextState: PROCESS(CLK) IS
        VARIABLE NS: STATE;
        VARIABLE OP: OPCODE;
        VARIABLE F:  FUNC;
    BEGIN
        IF CLK'EVENT and CLK = '0' THEN -- Falling edge
            IF RES = '1' THEN
                NS := S0;
            ELSE
                OP := IR(31 DOWNTO 26);
                F  := IR(5 DOWNTO 0);   
                CASE NS IS
                    WHEN S0 =>      -- FETCH
                        NS := S1;
                    WHEN S1 =>      -- DECODE
                        CASE OP IS
                            WHEN OP_LW | OP_SW =>
                                NS := S6;
                            WHEN OP_r_TYPE =>
                                NS := S4;
                            WHEN OP_BEQ =>
                                NS := S3;
                            WHEN OP_J =>
                                NS := S2;
                            WHEN OTHERS =>
                                NS := S0;
                        END CASE;                                                
                    WHEN S6 =>
                        CASE OP IS
                              WHEN OP_LW =>
                                    NS := S7;
                              WHEN OP_SW =>
                                    NS := S8;
                              WHEN OTHERS =>
                                    NS := S0;
                        END CASE;                                                  
                    WHEN S7 =>
                        NS := S9;
                    WHEN S9 =>
                        NS := S0;
                    WHEN S8 =>
                        NS := S0;
                    WHEN S4 =>
                        NS := S5;
                    WHEN S5 =>
                        NS := S0;
                    WHEN S3 =>
                        NS := S0;
                    WHEN S2 =>
                        NS := S0;
                END CASE;
                S <= NS;
            END IF;
        END IF;            
    END PROCESS GetNextState;
END ARCHITECTURE behav;