---------------------------------------------------------------------
-----------
-- Function: tband2.vhd - Test bench for aand2.vhd.
-- Requires: and2.vhd, pkgmips.vhd
-- Author:   
-- Creation: 
-- Verified: 
-- Version:  
---------------------------------------------------------------------
------------
use work.mips.all;
library IEEE;                -- Make IEEE lib visiable
use IEEE.std_logic_1164.all; -- Select package std_logic_1164

ENTITY tb IS END tb;

ARCHITECTURE test OF tb IS
-- Component declarations
	COMPONENT and2 IS
	    GENERIC(trise : delay := 10 ns;
	            tfall : delay := 28 ns);
	    PORT(a : IN std_logic;
	         b : IN std_logic;
	         c : OUT std_logic);
	END COMPONENT;
-- Signal declarations
	SIGNAL a, b: std_logic;
	SIGNAL y: std_logic;

BEGIN
	and_gate: and2 PORT MAP(a => a, b => b, c => y);

    PROCESS
        CONSTANT period: time := 40 ns;
    BEGIN
	WAIT FOR period;
        a <= '0';
        b <= '0';
        WAIT FOR period;
            ASSERT (y = '0')
            REPORT "Test failed!" SEVERITY ERROR;
        a <= '0';
        b <= '1';
        WAIT FOR period;
            ASSERT (y = '0')
            REPORT "Test failed!" SEVERITY ERROR;
        a <= '1';
        b <= '1';
        WAIT FOR period;
            ASSERT (y = '1')
            REPORT "Test failed!" SEVERITY ERROR;
        a <= '1';
        b <= '0';
        WAIT FOR period;
            ASSERT (y = '0')
            REPORT "Test failed!" SEVERITY ERROR;
        WAIT;
    END PROCESS;
END TEST;