---------------------------------------------------------------------
-----------
-- Function: tbPC - Test bench for PCreg.
-- Requires: pc.vhd;
-- Author:   Jerry H. Tucker
-- Creation: 9/20/99
-- Verified: 9/20/99
-- Version:  1.0
----------------------------------------------------------------------
------------
LIBRARY IEEE;
USE work.mips.all;
USE work.all;
USE IEEE.Std_Logic_1164.all; 
USE IEEE.std_logic_unsigned.all;

ENTITY tbpc is END tbpc ;

ARCHITECTURE behav OF tbpc IS
   SIGNAL PC   : std_logic_vector(CWordSize-1 downto 0);
   -- Note how Addr is initilized to all 0's.
   SIGNAL Addr : std_logic_vector(CWordSize-1 downto 0) := (OTHERS => 
'0');
   SIGNAL C    : std_logic := '0';
   SIGNAL LD   : std_logic := '0';
   SIGNAL R    : std_logic := '1';
BEGIN
    U1: ENTITY PCreg(behav)
    PORT MAP(C, R, LD, Addr, PC);
    C <= NOT C after 50 ns;
    R <= '0' after 110 ns;
    LD <= '1' after 310 ns, '0' after 360 ns;
END behav;