-- tbmod10.vhd Version 2.0 by Dr. Jerry H. Tucker
-- Created  9/25/00 Worked     
-- entities TBmod10
-- Uses swclk in swclk.vhd
--      cmtmod10 in cntmod10.vhd
LIBRARY IEEE;
USE work.all;
USE IEEE.Std_Logic_1164.all; 
use ieee.numeric_std.all;
-----------------------------------------------------------------------
--  ENTITY: TBMOD10 - Test bench for CNTMOD10.VHD
--    PORT: None   
--   NEEDS: swclk, cntmod10 in cntmod10.vhd
-----------------------------------------------------------------------
ENTITY TBmod10 IS
END ENTITY TBmod10;

ARCHITECTURE TEST OF TBmod10 IS
    SIGNAL CLK: std_logic;
    SIGNAL Res: std_logic := '1';
    SIGNAL EN: std_logic := '0';
    SIGNAL QOUT: std_logic_vector(3 downto 0);
BEGIN         
    Res <= '0' after 25 ns, '1' after 330 ns;
    EN <= '1' after 15 ns, '0' after 45 ns, '1' after 75 ns;
    CLK2: ENTITY work.swclk(behav)
            GENERIC MAP(period => 10 ns)
            PORT MAP(CLK => CLK);
            
    DUT: ENTITY cntmod10    
        PORT MAP
         (CE => EN,             -- Always enable counting
          CLK => CLK,           -- Clock at 100 MHz 
          CLR => Res,           -- Reset for 25 nsec
          QOUT => QOUT          -- Signal to drive ones LED
         );
END ARCHITECTURE TEST;