-- tbalu.vhd Version 1.0 by Dr. Jerry H. Tucker
-- Created  10/2/00    
-- entities TBdemo
-- Uses alu in alu.vhd
LIBRARY IEEE;
USE work.all;
USE IEEE.Std_Logic_1164.all; 
USE IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------
--  ENTITY: TBalu - First Test bench for alu  
-- GENERIC: None
--    PORT: None   
--   NEEDS: alu
-------------------------------------------------------
ENTITY TBalu IS
END ENTITY TBalu;

ARCHITECTURE TEST OF TBalu IS
    SIGNAL A: std_logic_vector(1 downto 0) := "11";
    SIGNAL B: std_logic_vector(1 downto 0) := "11";
    SIGNAL Func: std_logic_vector(2 downto 0) := "000";
    SIGNAL InvB: std_logic := '0';
    SIGNAL Rout: std_logic_vector(1 downto 0);
    SIGNAL Cin2, MSSet, Ov, Z1: std_logic;
BEGIN         
    A(1 downto 0) <= A(1 downto 0) + 1 after 10 ns;
    B(1 downto 0) <= B(1 downto 0) + 1 after 50 ns;
Func <= "000",              -- and
            "001" after 200 ns, -- or
            "010" after 400 ns, -- add
            "110" after 600 ns, -- subtract
            "111" after 800 ns; -- set on less than
 -- Least significant slice
MyNew: PROCESS (Func)
	BEGIN
		IF (Func = "110") OR (Func = "111") THEN
			InvB <= '1';
		ELSE
			InvB <= '0';
		END IF;
	END PROCESS MyNew;
    ALU1: ENTITY work.alu(behav)
            GENERIC MAP (Slice => 2) 
            PORT MAP
            (
                Ain => A(1 downto 0),
                Bin => B(1 downto 0),
                Cin => InvB,
                Result => Rout(1 downto 0),
                Cout => Cin2,
                Operation => Func,
                Binvert => InvB,
                Less => MSSet,
                Set => MSSet,
                Overflow => Ov,
                Zero => Z1
            );
END ARCHITECTURE TEST;