-- bigalu.vhd 
--  Worked     
-- entities BigALU
-- Uses alu in alu.vhd
LIBRARY IEEE;
USE work.all;
USE work.mips.all;
USE IEEE.Std_Logic_1164.all; 
--USE IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-----------------------------------------------------------------------
--  ENTITY: BigALU - Connects 4 ALU slices together to form a complete
--          ALU.
-- GENERIC: Width - The size of BigALU the default is DWordSizr.
--          Width will me a multiple of 4 greater than 4.
--    PORT: SA - A input to the BigALU
--          SB - B input to the BigALU
--          ALU - Output of BigALU
--          Func - Function to be performed by BigALU.
--                      "000" - and
--                      "001" - or
--                      "010" - add
--                      "110" - subtract
--                      "111" - set on less than
--           Overflow - Overflow signal
--           Zero     - If all bits of ALU = 0 then Zero = '1' 
--                      else Zero = '0'
--   NEEDS: alu in alu.vhd
-----------------------------------------------------------------------
ENTITY BigALU IS
    GENERIC(Width: Integer := DWordSize);
    PORT(SA, SB:    IN std_logic_vector(Width - 1 downto 0);
        ALU:        OUT std_logic_vector(Width - 1 downto 0);
        Func:       IN std_logic_vector(2 downto 0);
        Overflow:   OUT std_logic;
        Zero:       OUT std_logic
        );
END ENTITY BigALU;

ARCHITECTURE Struc OF BigALU IS
    CONSTANT Swidth: INTEGER := Width/4;
    SIGNAL InvB : std_logic;
    SIGNAL Z : std_logic_vector(dwordsize-1 downto 0) := (others => '0');
    SIGNAL SetLess : std_logic;
    SIGNAL Ca : std_logic; 
    SIGNAL Cb : std_logic;
    SIGNAL Cc : std_logic;
    SIGNAL Cd : std_logic;
  
   
BEGIN  

    Zero <= Z(0) and Z(1) and Z(2) and Z(3);
    

    PROCESS(Func) 
    BEGIN
        IF (Func = "110") OR (Func = "111") THEN
            InvB <= '1';
        ELSE
            InvB <= '0';
        END IF;        
    END PROCESS ;
  
 -- Least significant slice of ALU
    ALU0: ENTITY work.alu(behav)
            GENERIC MAP (Slice => 2) 
            PORT MAP
            (
                Ain => SA(Swidth - 1 downto 0),
                Bin => SB(Swidth - 1 downto 0),
                Cin => InvB,
                Result => ALU(Swidth - 1 downto 0),
                Cout => Ca,
                Operation => Func,
                Binvert => InvB,
                Less => SetLess,
		Zero => Z(0)
            );
    ALU1: ENTITY work.alu(behav)
            GENERIC MAP (Slice => 2) 
            PORT MAP
            (
                Ain => SA(2*Swidth - 1 downto Swidth),
                Bin => SB(2*Swidth - 1 downto Swidth),
                Cin => Ca,
                Result => ALU(2*Swidth - 1 downto Swidth),
                Cout => Cb,
                Operation => Func,
                Binvert => InvB,
                Less => '0',
                Zero => Z(1)
            );
    ALU2: ENTITY work.alu(behav)
            GENERIC MAP (Slice => 2) 
            PORT MAP
            (
                Ain => SA(3*Swidth - 1 downto 2*Swidth),
                Bin => SB(3*Swidth - 1 downto 2*Swidth),
                Cin => Cb,
                Result => ALU(3*Swidth - 1 downto 2*Swidth),
                Cout => Cc,
                Operation => Func,
                Binvert => InvB,
                Less => '0',
                Zero => Z(2)
            );
 -- Most significant slice of ALU
    ALU3: ENTITY work.alu(behav)
            GENERIC MAP (Slice => 2) 
            PORT MAP
            (
                Ain => SA(4*Swidth - 1 downto 3*Swidth),
                Bin => SB(4*Swidth - 1 downto 3*Swidth),
                Cin => Cc,
                Result => ALU(4*Swidth - 1 downto 3*Swidth),
                Cout => Cd,
                Operation => Func,
                Binvert => InvB,
                Less => '0',
                Set => SetLess,
                Overflow => Overflow,
                Zero => Z(3)
            );
END ARCHITECTURE Struc;