-- swclk.vhd Version 1.0 by Dr. Jerry H. Tucker
-- Created  9/25/99 Worked     
-- entities swqclk
-- Uses     NONE
LIBRARY IEEE;
USE work.all;
USE IEEE.Std_Logic_1164.all; 
USE IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
------------------------------------------------------------------------
-- ENTITY:  SWCLK - Generates square wave  CLK starting at t=0.
--          CLK = '0' for 1/2 Period then  CLK = '1' for 1/2 Period.
-- GENERIC: period - Period of CLK defaultts to 10 ns = 100 MHz.
-- PORT:    CLK - Square wave clock outputt.
-- NEEDS:   NONE
-- USSAGE:  In VHDL-93 See tbdemo.vhd
--          U1: ENTITY work.swclk(behav)
--                  GENERIC MAP(period =>  20 ns)
--                  PORT MAP(Q => TBQ);
------------------------------------------------------------------------
ENTITY swclk IS
    GENERIC(period : time := 10 ns); -- Default to 100 MHz
    PORT(   Clk : OUT std_logic);
END ENTITY swclk;

ARCHITECTURE behav OF swclk IS
    SIGNAL Qsig: std_logic := '0'; -- Declare new signal so Clk can be OUT
BEGIN
    Qsig <= not Qsig AFTER period/2;
    Clk <= Qsig;
END ARCHITECTURE behav;