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-- Function: and2.vhd - Simple two input  and gate using 
--           standard logic
-- Requires: pkgmips.vhd
-- Author:   
-- Creation: 
-- Verified: 
-- Version:  
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-- entity:  and2  - Two input and gate
-- generic: trise - Rise time gate delay  see pkgmips.vhd
--          tfall - Fall time gate delay  see pkgmips.vhd
-- port:    a, b  - Inputs to and2 gate
--          c     - Output of and2 gate
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USE work.mips.all;
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY and2 is
    GENERIC(trise : delay := 10 ns;
            tfall : delay := 8 ns);
    PORT(a : IN std_logic;
         b : IN std_logic;
         c : OUT std_logic);
END and2;

ARCHITECTURE behav OF and2 IS
BEGIN
    one : PROCESS (a,b)
    BEGIN
        IF (a = '1' AND b = '1') THEN
            c <= '1' AFTER trise;
        ELSIF (a = '0' OR b = '0') THEN
            c <= '0' AFTER tfall;
        ELSE
            c<= 'X' AFTER (trise+tfall)/2;
        END IF;
    END PROCESS one;
END behav;