--tbcufsm.vhd Version 1.0 by David Staples and Josh Bell
--Created Spring 2000
--entities cufsm.vhd
LIBRARY IEEE;
USE work.all;
USE work.mips.all;
USE IEEE.Std_Logic_1164.all;
USE IEEE.std_logic_signed.all;
use ieee.std_logic_arith.all;
---------------------------------------------------
-- ENTITY: tbcufsm - Test bench for cufsm
-- GENERIC: None
-- PORT: IN S -State of FSM
--	 OUT CLK - Clock falling edge
--	 OUT RES - Reset signal
--	 OUT IR - Instruction Register
-- NEEDS: cufsm in cufsm.vhd
---------------------------------------------------
ENTITY tbcufsm IS
END ENTITY tbcufsm;

ARCHITECTURE TEST OF tbcufsm IS
	SIGNAL CLK: std_logic := '0';
	SIGNAL RES: std_logic := '0';
	SIGNAL IR: std_logic_vector(CWordSize - 1 downto 0);
	SIGNAL S: STATE;
BEGIN
	RES <= '1' after 10 ns,
	       '0' after 20 ns;
	IR <= "00000000000000000000000000010000" after 10 ns, --add
	      "00000000000000000000000000010010" after 50 ns, --sub
	      "00000000000000000000000000000100" after 90 ns, --slt
	      "00000000000000000000000000010101" after 130 ns, --or
	      "00000000000000000000000000011010" after 170 ns, --and
	      "10001100000000000000000000000000" after 210 ns, --lw
	      "10101100000000000000000000000000" after 260 ns, --sw
	      "00010000000000000000000000000000" after 300 ns, --beq
	      "10000000000000000000000000000000" after 330 ns; --j
	CLK <= not CLK after 5 ns;
	DUT: ENTITY cufsm
		PORT MAP
		(CLK => CLK,
		 RES => RES,
		 IR => IR,
		 S => S
		);
END ARCHITECTURE TEST;