----------------------------------------------------------------------
-- File:     PCreg - PC register
-- Author:                    <--- PUT your name here
-- Creation: 9/19/99
-- Verified:                  <--- Make any necessary changes           
-- Version:  1.0
------------------------------------------------------------------------
-- Requires: pkgmips.vhd
LIBRARY IEEE;
USE work.mips.all;
USE IEEE.Std_Logic_1164.all; 
USE IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
------------------------------------------------------------------------
-- FUNCTION: PCreg  - PC register
--   INPUTS: Clk - Clocks PC on falling eddge
--           Res - Asyncronous reset. PC rremains 0 as long as Res = 1. 
--           LD  - If 1 when clocked PC looaded from Addr 
--                 else PC is incremented  by 4
--           Addr - Load value to PC
--  OUTPUTS: PC  - Program counter registeer for MIPS
------------------------------------------------------------------------
ENTITY PCreg IS
     PORT(Clk, Res, LD: IN std_logic;
          Addr: IN std_logic_vector(CWordSize-1 downto 0);
          PC: BUFFER std_logic_vector(CWordSize-1 downto 0));
END ENTITY PCreg;

ARCHITECTURE behav OF PCreg IS
BEGIN
    PROCESS(CLK, Res, LD) is
    BEGIN
        IF (Clk'EVENT AND Clk = '1') THEN
            PC <= PC + 4; -- This works because of IEEE.std_logic_arith
        END IF;
    END PROCESS;
END ARCHITECTURE behav;