-- cntmod10.vhd Version 2.0 by Dr. Jerry H. Tucker Modified by "David S"
-- Created  9/25/00 with no errors     
-- ENTITIES Mod10
-- Uses     NONE
LIBRARY IEEE;
USE work.all;
USE IEEE.Std_Logic_1164.all; 
USE IEEE.std_logic_unsigned.all;
------------------------------------------------------------
--  ENTITY: CntMod10 - Mod 10 binary counter.
-- GENERIC: NONE
-- PORT:    
--      IN: CE  - Chip Enable must be '1' to count.
--          CLK - Falling edge of CLK increments Qout.
--          CLR - CLR = 1 resets and holds Qout in 0 state.
--     OUT: QOUT- Fout bit binary count.
--   NEEDS: NONE
------------------------------------------------------------
entity CntMod10 is
    port (  CE : in STD_LOGIC;
            CLK : in STD_LOGIC;
            CLR : in STD_LOGIC;
            QOUT : out STD_LOGIC_VECTOR(3 downto 0)
         );
end ENTITY CntMod10;

architecture syn of CntMod10 is
    signal qoutsig : STD_LOGIC_VECTOR(3 downto 0);
begin
    process(CLK,CLR)
    begin
        if(CLR='1') then
            qoutsig <="0000";
	    QOUT <= qoutsig;
        elsif(CE='1' and qoutsig >= "1001") then
            if(CLK'event and CLK='0') then 
                qoutsig <= "0000";
		QOUT <= "0000" ;
	    end if;
	elsif(CE='1' and CLK'event and CLK='0') then
	        qoutsig <= qoutsig + "0001";
		QOUT <= qoutsig + "0001"; 
	    
        end if;
	 
    end process;
end ARCHITECTURE syn;