On Paul's system, each MMU address selects a standard $2000 block of RAM. Since the MMU registers are 8 bit lines they only address $FF*$2000 or $1FE000. The address needs to be extended for two more bits at $FF9B to get $400*$2000 or $800000. Here is how I would describe the system.

1) The video bits (xxmmvvvv) at $FF9B have immediate effect and are used in conjunction with the video offset registers $FF9D-$FF9E. The combined registers create a pseudo 20 bit register. This enables access to 1,048,576 (2^20) video offset locations. Since the offsets are separated by 8 bytes, this covers 8* 2^20 = 8,388,608 (8Meg).

2) The memory bits (xxmmvvvv) at $FF9B have no effect until a value is sent to an MMU register, $FFA0-$FFAF. When a value is sent to an MMU register, the memory bits at $FF9B combine with the MMU register to create a pseudo 10 bit register. This enables access to 1024 (2^10) MMU blocks for a total memory of 1024*8192=8,388,608 (8Meg).

3) The value at $FF9B is latched and therefore stable but is write only as are the two high bits in the MMU registers.

Paul is able to run OS-9 Level II on the system, but I believe he needed to change the manner in which the memory bits were processed. There are more details on his web page describing how to keep the DRAM at $xFExx constant.

It was a real challenge to write code for this system without having the hardware for testing. However, the programs were valuable as they permitted Paul to determine that two bits of the Lattice CPLD schematic were reversed. Reprogramming resulted in contiguous memory as indicated by the Vidtest program.
 

"L. Curtis Boyle" wrote:
>
> On Fri, 12 Nov 1999, Robert Gault wrote:
>
> > One important caveat!! The program is written using 6309 code. It
> > won't run on a 6809 system!
> >
> > The program can test memory on systems having 128K, 512K, 1Meg,
> > 2Meg, 4Meg, 6Meg, and 8Meg if, and this is a big if, it conforms to
> > the format used by Paul to install the extra memory. The two high
> > bits of $FFA0-$FFAF pull in memory from 512K up to 2Meg. $FF9B is
> > used to access memory from 2Meg up to 8Meg. See Paul's web page for
> > details.
>      Out of curiousity, does this mean that, to access memory >2MB, you must
> switch the ENTIRE 2MB out at a time (ie, you can't mix 8K MMU blocks from
> different 2 MB chunks)? If so (and I can't see how you would get around it
> without using 16 more memory addresses), it would be a little difficult to get
> it working under OS9 smoothly. Also, the 256 byte vector page (if enabled) -
> does it always take from the same 2 MB chunk, or is it also dependent on which
> 2 MB block you are specifiying in $ff9b?
 

Being a diehard Cocoist, I obtained an 8 Meg board from Paul T. Barton ( the second production unit I believe.) While installation is not for the timid, all went well and I now have an 8 Meg Coco3 which can run at 4 MHz using a 63B09. I have chosen to stay with standard clock speeds for now.

I am pleased to be able to recommend the high quality of the NoCan3 PC board and report that Paul has done a superb job with his project. Without making any changes to my NitrOS9 software, the new system reports 2 Meg memory. My RGB-DOS hard drive ROM Basic system is also happy with the new hardware.
 

A 2MB interface is not needed, this board emulates the original 2MB interface.
All 2MB bits work as before, no changes.

For NitrOS-9 users, no changes are required to use the 2MB.

For OS9 users, you must patch the system for the 2MB to be useable.

Test Video Memory (8MB):

This is immediate.

1. Write page # to $FFA?, lower 6 bits only.
2. Write page # to #FF9B, bits 3 to 0, only.

1. and 2. are not sequence dependant, 2 can be executed before 1.

Sequence:
Bits of $FFA? go from %00000000 to %00111111
Bits of $FF9B go from %00000000 to %00001111

Or:
Bits of $FF9B go from %00000000 to %00001111
Bits of $FFA? go from %00000000 to %00111111

Test CPU memory (8MB):

This is sequence dependant!

Only $FF9B bits 4 & 5 are sequence dependant,
ALL other bits are immediate.

1. Write page bits to $FF9B, bits 4 and 5 only.
2. Write page bits to $FFA? all 8 bits.
     When this write occurs the $FF9B bits 4 & 5 are then written
     to the SRAM page that matches the $FFA? page.
3. Change the $FF9B bits 4 & 5 before writing to any more $FFA? pages.

As the $FFA? pages are used,
all 10-bits are there allowing any accesses in the 8MB space, anywhere.

Sequence:
Bits of $FF9B go from %00xx0000 to %00110000
Bits of $FFA? go from %00000000 to %11111111

 * Thanks from all of us to the many contributors who shall remain unknown! *

 -----------------------------------------------------------------------------
 I        COCO-3 MEMORY, and GIME REGISTER MAP   (1 Sept 86)  KD ver1        I
 -----------------------------------------------------------------------------

SYSTEM MEMORY MAP:
 RAM      00000 - 7FFFF 512K bytes
 ROM      78000 - 7FEFF when enabled
 I/O      XFF00 - XFFFF I/O space and GIME regs

64K PROCESS MAP:
 RAM       0000 - FEFF (possible vector page FEXX)
 I/O       FF00 - FFFF (appears in all pages)

Note: the Vector Page RAM at 7FE00 - 7FEFF, when enabled, will appear instead
 of the RAM or ROM at XFE00 - XFEFF. (see FF90 Bit 3)

  XFF00-0X  PIA0        (not fully decoded)
  XFF10-1F  reserved    (NoCan(x): 16550, 6551A & 6821 I/O)
  XFF20-2X  PIA1        (not fully decoded)
  XFF30-3F  reserved
  XFF40-5F  SCS         (see note on FF90 Bit 2)
  XFF60-7F  undecoded   (for current peripherals)
  XFF80-8F  reserved
 ===============================================================================

 FF90  INITIALIZATION REGISTER 0
        Bit 7 - CoCo Bit  1= Color Computer 1/2 Compatible 
        Bit 6 -           1= MMU enabled
        Bit 5 -           1= GIME IRQ output enabled to CPU
        Bit 4 -           1= GIME FIRQ  "      " 
        Bit 3 -           1= Vector page RAM at FEXX enabled
        Bit 2 -           1= Standard SCS
        Bit 1 -           ROM mapping      0 X - 16K internal, 16K external
        Bit 0 -            "    "          1 0 - 32K internal
                                           1 1 - 32K external

 CoCo bit set = MMU disabled, Video address from SAM, RGB/Comp Palettes = CC2.
 Interrupt bits 5 and/or 4 must be set for FIRQ/IRQ FF92-3 to pass to CPU.
 Access and moves throughout mem are usually done from constant RAM at FEXX.
 If Bit2=0, then XFF50-5F is SCS, and XFF40-4F will be internal to CoCo.
 -------------------------------------------------------------------------------

 FF91  INITIALIZATION REGISTER 1
        Bit 6 -           0=64K chips, 1 = 256K chips
        Bit 5 - TINS      Timer INput Clock Select:  0= 70 nsec, 1= 63 usec
        Bit 0 - TR        MMU Task Register Select (0/1 - see FFA0-AF)
 -------------------------------------------------------------------------------

 FF92  IRQENR   Interrupt Request Enable Register (IRQ)
 FF93  FIRQENR   Fast Interrupt Request Enable Reg (FIRQ)
   (Note that the equivalent interrupt output enable bit must be set in FF90.)
   Both registers use the following bits to enable/disable device interrupts:
       Bit 5 - TMR        Timer
       Bit 4 - HBORD      Horizontal border
       Bit 3 - VBORD      Vertical border
       Bit 2 - EI2        Serial data input
       Bit 1 - EI1        Keyboard
       Bit 0 - EI0        Cartridge (CART)

   I have no idea if both IRQ & FIRQ can be enabled for a device at same time.
 -------------------------------------------------------------------------------

 FF94  Timer MSB    Write here to start timer.
 FF95  Timer LSB
  Load starts timer countdown. Interrupts at zero, reloads count & continues.
  Must turn timer interrupt enable off/on again to reset timer IRQ/FIRQ.

 FF96  reserved.
        NoCan3-B Write-Only Latched Bits:
         Bit_0 : 1= Turbo on, 0= Turbo off. (4MHz)
         Bit_1 : 1= Long, 0= Short.
         Bit_2 : 1= Phase Shift, 0= Normal Position.
 FF97  reserved.
 -------------------------------------------------------------------------------

 FF98  Alpha/graphics Video modes, and lines per row.
        Bit 7 = vidmode  0 is alphanumeric, 1= bit plane (graphics)
        Bit 6 = na       ...
        Bit 4 = MOCH     MOnoCHrome bit (composite video output) (1=mono)
        Bit 5 = DESCEN   1= extra DESCender ENable
        Bit 3 = H50      50hz vs 60hz bit
        Bit 2 = LPR2     Number of lines/char row:
        Bit 1 = LPR1      (Bits 2-1-0 below:)
        Bit 0 = LPR0
                         000 - 1 line/char row    100 - 9  lines/char row
                         001 - 2                  101 - 10
                         010 - 3                  110 - 11 (??)
                         011 - 8                  111 - 12 (??)
 -------------------------------------------------------------------------------

 FF99  VIDEO RESOLUTION REGISTER
        Bit 7 - na     ...                            (bits 6-5):
        Bit 6 - LPF1   Lines Per Field:       00= 192 lines    10= 210 lines
        Bit 5 - LPF0     "    "    "          01= 200 lines    11= 225 lines
        Bit 4 - HR2    Horizontal Resolution
        Bit 3 - HR1         "        "
        Bit 2 - HR0         "        "        (see below for HR, CRES bits)
        Bit 1 - CRES1  Color RESolution bits
        Bit 0 - CRES0     "      "
 ---------------------------------------------
 TEXT MODES:

 Text: CoCo Bit= 0 and FF98 bit7=0.  CRES0 = 1 for: attribute bytes are used.

                      HR2 HR1 HR0    (HR1 = don't care for text)
        80 char/line   1   X   1 
        64     "       1   X   0 
        40     "       0   X   1 
        32     "       0   X   0 

 ---------------------------------------------
 GRAPHICS MODES:

         X   Colors   HR2 HR1 HR0  CRES1 CRES0
        640    4   -   1   1   1      0   1
        640    2   -   1   0   1      0   0

        512    4   -   1   1   0      0   1 
        512    2   -   1   0   0      0   0 

        320   16   -   1   1   1      1   0         Other combo's are
        320    4   -   1   0   1      0   1         possible, but not
        320    2   -   0   1   1      0   0         supported.

        256   16   -   1   1   0      1   0
        256    4   -   1   0   0      0   1
        256    2   -   0   1   0      0   0

        160   16   -   1   0   1      1   0

 Old SAM modes work if CC Bit set. HR and CRES are Don't Care in SAM mode.
 Note the correspondence of HR2 HR0 to the text mode's bytes/line.
 Also that CRES bits shifted left one = number of colors. --Kev
 -------------------------------------------------------------------------------

 FF9A  Border Palette Register (XX00 0000 = CoCo 1/2 compatible)
 FF9B  Reserved.
        1MB and 2MB bits, Write only.
        Bit 7 - na
        Bit 6 - na
        Bit 5 - 8MB Memory Bit          NoCan3 bits for 8MB. 
        Bit 4 - 4MB Memory Bit          NoCan3 bits for 8MB. 
        Bit 3 - 8MB Video Bit           NoCan3 bits for 8MB. 
        Bit 2 - 4MB Video Bit           NoCan3 bits for 8MB. 
        Bit 1 - 2MB Video Bit   Disto & NoCan2/3 bits for 2MB. 
        Bit 0 - 1MB Video Bit   Disto & NoCan2/3 bits for 1MB.

 FF9C  Vertical Fine Scroll Register 
 FF9D  Screen Start Address Register 1 (bits 18-11)
 FF9E  Screen Start Address Register 0 (bits 10-3)
 FF9F  Horizontal Offset Register 
        Bit 7 - horizontal offset enable bit (128 char width always) 
        Bit 6 - X6  ... offset count (0-127)
        Bit 5 - X5    for column scan start.
        Bit 4 - X4
        Bit 3 - X3
        Bit 2 - X2
        Bit 1 - X1
        Bit 0 - X0

 If Bit 7 set & in Text mode, then there are 128 chars (only 80 seen)/line.
 This allows an offset to be specified into a virtual 128 char/line screen, 
  useful for horizontal hardware scrolling on wide text or spreadsheets.
 -------------------------------------------------------------------------------

 FFA0-AF  MEMORY MANAGEMENT UNIT (MMU)
  FFA0-A7  Task #0 Map Set  (8K block numbers in the 64K map)
  FFA8-AF  Task #1 Map Set  (Task map in use chosen by FF91 Bit 0)

 If you don't know what a DAT or MMU is, read CCRAM.TXT in DL6 of OS9 SIG.

 Each register has 6 bits into which is stored the block number 0-63 ($00-$3F)
  of the Physical 8K RAM block (out of 512K) that you wish to appear at the
  CPU Logical address corresponding to that register.
 Also can be shown this way: the 6 register bits, when the Logical Address in
  the range of that register, will become the new Physical RAM address bits:
         18  17  16   15  14  13 

  MMU Register:          CPU:
   Task0  Task1    Logical Address / Block#
    FFA0   FFA8     0000 - 1FFF      0         The 6-Bit Physical Block Number
    FFA1   FFA9     2000 - 3FFF      1          placed in a MMU register will
    FFA2   FFAA     4000 - 5FFF      2          become the A13-A18 lines when
    FFA3   FFAB     6000 - 7FFF      3          the corresponding Logical Add
    FFA4   FFAC     8000 - 9FFF      4          is accessed by the CPU.
    FFA5   FFAD     A000 - BFFF      5
    FFA6   FFAE     C000 - DFFF      6
    FFA7   FFAF     E000 - FDFF      7

 -------------------------------------------------------------------
 Ex: You wish to access Physical RAM address $35001. That Address is:

 A- 18  17  16  15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0
    .....3....  .......5......  .......0......  .......0......  .......1......
     0   1   1   0   1   0   1   0   0   0   0   0   0   0   0   0   0   0   1

 Taking address bits 18-13, we have: 0 1 1 0 1 0, or $1A, or 26. This is the
 physical RAM block number, out of the 64 (0-63) available in a 512K machine.

 Now, let's say you'd like to have that block appear to the CPU at Logical
  Block 0  (0000-1FFF in the CPU's 64K memory map).

 You would store the Physical Block Number ($1A) in either of the two Task Map
  registers that are used for Logical Block 0 (FFA0 or FFA8). Unless your pgrm
  doing this is in the Vector RAM at FEXX (set FF90 Bit 3, so ALWAYS there),
  you would want to use your current Task Map Register Set. If the TR bit at
  FF91 was 0, then you'd use MMU register FFA0 for the $1A data byte.

 To find the address within the block, use Address Bits 12-0 plus the Logical
  base address (which in this case is $0000):
 Now you could read/write address $1001, which would actually be $35001.
 ------------------------------------------------------------------------------

 FFB0-BF  COLOR PALETTE REGISTERS  (6 bits each)
  FFB0 - palette 0
  FFB1 - palette 1        The pixel or text attribute bits in video memory
  ...                      form the address of a color palette (0-15).
  FFBF - palette 15       It is the color info in that palette which is seen.

  Reg bits- 5  4  3  2  1  0
  CMP ...  I1 I0 P3 P2 P1 P0    Intensity and Phase (16 colors x 4 shades)
  RGB ...  R1 G1 B1 R0 G0 B0    Red Green Blue      (64 RGB combo's)

  When CoCo Bit is set, and palette registers preloaded with certain default
values (ask, if you need these), both the RGB and CMP outputs appear the same 
color, supposedly.

  40/80 Column Text Screen Bytes are Even=char, Odd=attribute, in memory. 
  Characters selected from 128 ASCII.  NO text graphics-chars.

  Char Attributes- 8 bits...  F U T T T B B B
       Flashing, Underline, Text foregrnd, Backgrnd colors 0-7.
 ------------------------------------------------------------------------------

 FFC0-DF  SAM : same as before (mostly compatible Write-Only Switches)
  FFD8 = CPU .895 MHz   (no address-dependent speed)
  FFD9 =     1.79 MHz
  FFDE = Map RAM/ROM    (RAM accesses use MMU translations)
  FFDF =     all RAM
 ------------------------------------------------------------------------------