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Presented by: Only On Saturday Night

Note #1: Testing so far has revealed that the 4MHz circuit may not work at all or in all applications. So, for this reason, it is not guaranteed. I'm sorry that this is the case, for now. Hopefully further testing will reveal what is going on. So far, it works great on re-packs.

    Of all the coco-3 motherboards that I have (about 7-8 or so), none fail in either of 8MB or Turbo. Most all of my boards are re-packs, meaning that the motherboards have been converted to run on PC-XT power-supplies. This is the only difference that I can see, so far. They run and boot NitrOS-9 in Turbo from a cold-power-up directly into IDE NitrOS-9 (from a standard 360K floppy & controller).



Note #2: 16550 and 6551 only have TXD, RXD, RTS and CTS connected to the MAX232 RS-232 buffer. Other RS-232 control signals are permanently tied to the proper voltage levels for operation. However, an additional MAX2332 (Dallas232) can be piggy-backed, connecting only pins 2,6,15 & 16 to the lower MAX232 (Dallas232). Now by hand-wiring, you can achieve DTR, DSR and DCD connections. Slight modifications are required to the NoCan board, i.e. cutting free pins 37 & 38 of the 16550 for this hand-wired mod. 6551A mods are probably similar with different pin #'s.


Also, after doing this mod, there's an extra RS-232 driver available. I tied two LED's to the RS-232 output and to ground. Pulling the input high lights one LED pulling the input low lights the other LED. Wire the LED's across each other, one forwards, one backwards. Tie one end of this pair to the RS-232 driver output and the other end to ground through a 2K resistor. Kind of a cheapie TTL probe. Will monitor any of the 16550 or 6551A driver/receiver TTL level lines for debugging, just hook it up.

Note #3: The CPU signal BS is now added to the 4MHz control inputs.

Note #4: A new register has been added. In the CPLD, Register $FF96 now gives you software control over the 4MHz activation. A NitrOS-9 program called "Turbo" does this for you. For instance, you type: "Turbo on". and off it goes! Alternately, you type : "Turbo off" and it goes off. For more info, see the NoCan3B page.
Bit 0 = 0, 4MHz, off.
Bit 0 = 1, 4MHz on.


Suggestions? -  Email me: 
 
$FF9B:
An 8-bit Latch.
76543210
||||||||
|||||||`.. 1MB Video Bit0
||||||`... 2MB Video Bit1
||||||
|||||`.... Video Bit2 (direct)
||||`..... Video Bit3 (direct)
|||`...... CPU Bit2   (sequenced)
||`....... CPU Bit3   (sequenced)
||
|`........ - nc (16MB, Video
`......... - nc (16MB, CPU 
Fully tested 11/11/1999

The Standard 1MB, 2MB access.

Now with 8MB access included.

$FFA0-$FFA7,
$FFA8-$FFAF.
DAT RAM,
Two pages of 16 bytes.
76543210
||||||||
|||||||`.. Standard GIME Access
||||||`... Standard GIME Access
|||||`.... Standard GIME Access
||||`..... Standard GIME Access
|||`...... Standard GIME Access
||`....... Standard GIME Access
||
|`........ CPU Bit0 (sram, 1MB)
`......... CPU Bit1 (sram, 2MB)
The Standard 1MB & 2MB access.

CPU Memory Software for 6309 MemTest.BIN by Robert Gault. Thanks Robert!
Now also for 6809, MemTest2.BIN.

This program tests all of the CPU memory and reports back if there are errors. It uses bit patterns $00, $AA, $55 and $FF for the testing.



Video Memory Software for 6309 VidTest.BIN by Robert Gault, is tested and works.  Thanks Robert!
Now also for 6809, VidTest2.BIN.

VIDTEST.BIN copies multiples of the ALT-CTRL-RESET image to memory. On each and every page at the bottom is the "PAGE IS AT $xxxxxx" in hexadecimal. It goes from $000000 to $7FE000 in $002000 steps. Using the UP/DOWN arrow keys allow you to page through memory to see the images and page numbers. Pages from $06C000 to $07E000 are RS-DOS system memory and show up but are not "pictures".


To use CPU (Memory) paging:
1. Disable interrupts.
2. Read the single $00FFAx, the single page to update, including bits 6 & 7. (512K chunks)
3. Write $00FF9B with the CPU data for the single $00FFAx page. Bits 4 & 5 only. (512K chunks)
4. Write back the single $00FFAx, the page to update. This write puts the CPU bits into SRAM.
5. (Write $00FF9B with previous CPU bits, else the next write access to $00FFAx will write the SRAM with two MSB's of page data.)
6. Enable interrupts.

Now that single page has all it's bits in that page's SRAM address.
Note: Every write to a single $00FFAx will write the current $00FF9B CPU bits (4 & 5) to that single $00FFAx location.



To use VIDEO paging:
1. Disable interrupts.
2. Write $00FF9B with the data. Bits 0 to 3. (changes video memory in 512K chunks)
3. Enable interrupts.


How it's connected:
The two VIDEO bits are just latched and then go directly to creating Address A10.

The two CPU bits get latched and then go to the SRAM data inputs addressed for $00FFAX, then return from the SRAM data outputs to create Address A10.
Whenever a write to $00FFAx is needed the two MSB's are first written to $00FF9B, then to $00FFAX. Then $FF9B is restored to the previous setting. If it is not restored, the next write to any $00FFAX changes that locations two MSB's.



Dreams:
Is 8MB the limit? How about 16MB? That would be 4 each 4MB 30-pin simms.
There's two more bits left in $FF9B and only two more are needed to get to 16MB.
BIT 6 would be the next Video bit.
BIT 7 would be the next CPU bit.


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