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SI Leader: Steve Naumov
Course: ECE 370: Digital Systems-Logic Design
Session: Wednesday, 12:00 pm - 2:00 pm, Room POT-213 & Friday, 11:00 am - 1:00 pm, Room POT-308
Office: Friday, 1:00 pm - 2:00 pm, Room GYTE-71
E-Mail: [email protected]
This page keeps an up-to-date log of the things that happen in the supplemental instruction session for ECE 370
at Purdue University Calumet. Below you will find notes, sample problems, and VHDL programs that explain and
demonstrate key digital systems analysis and design ideas, links to other web sites that explain digital logic
design topics, and other documents that might be pertinent to the SI Sessions (sample exams, quizzes, worksheets,
etc.).
When you are viewing any documents below, you can use your browser's "File -> Save As..." menu item
to save a copy of the file on your computer. It is a good idea for you to experiment with these
examples, as they will help you on your quizzes and/or exams.
Also, here is the Altera Software Download and Installation Instructions
This document contains step-by-step instructions on how to install MAX + PLUS II BASELINE 10.2
software and Quartus II 5.0 software by Altera Corporation.
Wednesday, May 4, 2005
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Here is a link to the sample exam for Chapter 8 as well as the Final Exam. We will be
discussing this sample exam at today's session and continue on Friday's session.
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The Final Review (Exam Jam) Session will be this Friday at 11 a.m and it
will end whenever everyone is comfortable with the material.
Friday, April 29, 2005
- Today, we will meet at 11 a.m in POT 308.
- Practice exam for Chapter 8 of the text will be finished shortly as well as a Practice Final exam.
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Today we discussed how to reverse engineer a FSM (Mealy & Moore) while also discussing
how to write VHDL code to implement FSM's.
Wednesday, April 27, 2005
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Today, we discussed three ways to assign bit values to states as well as applied those three
ways to a 2's complementor Moore FSM.
Friday, April 22, 2005
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Today, we discussed how to write VHDL code for Flip Flops and Registers. All code designed in
the session was printed out.
Wednesday, April 20, 2005
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Today, we will discuss how to analyze and design general circuits containing Flip Flops, not just
circuits that count or circuits that store n-bit data (registers). This
material is found in Chapter 8 of the textbook!
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Here is a link to the fourth mock exam on Chapter 7. It covers registers and register counters, which
is a special class of counters designed utilizing registers.
- Here is a link to a couple of quizzes on Chapter 8 material.
Friday, April 15, 2005
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Today we will continue to discuss how to design counters and then begin discussing registers, and
finally register-counters.
- Here is a list of links to quizzes concerning counters.
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Here is a link to the third mock exam for Chapter 7. It is about asynchronous and synchronous
counter design.
Wednesday, April 13, 2005
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Today's session and all subsequent Wednesday sessions will begin at 11:00 am due to time constraints.
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We will begin to discuss how to design asynchronous and synchronous binary counters.
Friday, April 8, 2005
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Today, we will continue discussing latches and flip-flops as the building blocks of sequential
circuits.
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Here is a link to the first two sample exams on Chapter 7. One covers Latches and the other
covers Flip-Flops.
Wednesday, April 6, 2005
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Today we will begin discussing sequential circuits and the main building blocks of sequential circuits.
- Here is a link to a very nice overview of of sequential circuits.
- Here is a link to quizzes involving Latches and Flip-Flops (FF's).
Friday, April 1, 2005
- Here are the links of all of the mock exams and quizzes pertaining to Chapters 5 and 6 of the text.
- Sample Quizzes 5
- Sample Exams-Chapter 5
- Sample Quizzes 6
- Sample Exams-Chapter 6
Wednesday, March 30, 2005
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Today we will continue discussing multiplexers and how to implement any combinational function them.
We also discussed the function of Demultiplexers.
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Here is a sample mock exam for the second part of Chapter 6: Multiplexers.
Friday. March 25, 2005
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Here is the sample mock exam for the first VHDL Lab Exam. Solutions will be handed out at the
end of the session and then posted online later this evening.
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Here is a sample mock exam for the first part of Chapter 6: Decoders and Encoders
Wednesday, March 23, 2005
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Today, we began discussing decoders, encoders, and multiplexers.
Specifically, we discussed the general functionality of the three
components, how to design them using gate-level implementations,
and how to analyze them. Also, we discussed how to implement SOP
and POS canonical functions using binary decoders.
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Here are a few quizzes on common combinational logic circuits.
Spring Break Meetings
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During the break, we focused on how to write structural and behavioral VHDL code to model arithmetic
circuits. Specifically, we designed components and packages for 1-bit adders and used them to create
multi-bit ripple-carry adders and ended with creating a generic n-bit ripple-carry adder.
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Here is a link to the first "real" VHDL exercise worksheet of the semester. It's purpose is
to give you a flavor of the types of questions to expect on the first lab exam.
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A mock lab exam session will be held in POT-308 on March 25, 2005 at 11:00 a.m. I will pass out the
mock-exam at that time, then post the exam and solutions online for your studying pleasure during
the weekend.
Friday, March 11
- Today, we continued working on the 3rd mock exam as a group, discussing
each problem in detail.
- We will meet at least 2 times during spring break. The schedule
is as follows:
- Tuesday, March 15 at 11:00 A.M. in POT-308
- Wednesday, March 16 at 11:00 A.M. in POT-308
Wednesday, March 9
- Today, we began working on the 3rd mock exam as a group, discussing
each problem in detail.
- Here is an updated list of exams. Thanks again to the Colorado
School of Mines for the questions for Parts 4 and 5 of Chapter 5's
sample exam with solutions.
Friday, March 4
- Today we continued our discussion of r and (r-1) complement schemes,
focusing on binary numbers. We also discussed overflow once again.
We began working on parts of the 2nd mock exam for Chapter 5.
- We will meet several times during spring break to prepare for
the lab exam the Monday and Tuesday after spring break.
- Here is a webiste that has really good notes on the whole course.
I use these notes from time to time to get ideas.
Wednesday, March 2
- Today, we briefly discussed unsigned subtraction with borrowing.
Then we moved on to unsigned number representations. We discussed
sign-magnitude, 1's complement, and 2's complement representations.
We briefly touched on general complement schemes ( r's complement
and (r-1)'s complement, where r is the radix of the number). Included
in the discussion was the concept of overflow.
- Here are all three ample (mock) exams for Chapter 5. These mock
exams are a bit on the challenging side, especially Part 3. We will
try to work on it together, but most of the work will come from
you guys!
Friday, February 25
- We will meet in POT-213 today until we finish discussing unsigned
binary addition and the hardware required to perform it. Then, we
will go to POT-308 to implement the hardware in VHDL. In lab, we
will discuss how to design in a hierarchical fashion using VHDL,
i.e. using smaller hardware pieces to build larger ones.
Wednesday, February 23
- Today, we discussed positional number systems, particularly the
meaning of a radix. The radices of particular interest are 2, 8,
and 16, or, binary, octal, and hexadecimal, respectively. We discussed
how to convert a decimal number into any radix and how to convert
a number in any radix into its decimal equivalent. We also discussed
counting in the major radices. We ended the session observing how
to add unsigned positional numbers together, focusing on binary
numbers.
- Here is the updated list of interactive quizzes, which includes
material from Chapters 2-5.
- Here is the first exercise in VHDL. It covers the topics that
we discussed on February 11. The exercise covers concurrent assignment
statements and the STD_LOGIC data type. Make sure you are able to
design both circuits all four different ways before the session
on Friday.
- Here are the links to all the mock exams so far. Most important
is the mock exam for Chapter 4.
- Here is a link to the University of Toronto's Digital Design Course.
The professor of the course is the author of our textbook. There
are links to solved problems, past midterm exams and solutions,
and past final exams and solutions. The exams are very useful. Make
sure you understand how to do all of the types of questions that
involve Chapters 2 and 4 ( i.e. anything with K-Maps, Boolean Algebra
and DeMorgan's laws, timing diagrams, design, NAND and NOR gates,
factoring, multiple output circuits, drawing logic networks, and
analysis of multi-level circuits).
Friday, February 18
- Today, we continued our discussion of NAND and NOR gates. We discussed
how design AND, OR, and NOT gates using NAND and NOR gates. We then
moved on to converting multi-level digital network to all NAND or
all NOR gates. We concluded our discussion with multiple output
circuits and the implication of using common minterms or maxterms
to implement multiple output networks. We compared and contrasted
implementing the functions separately and with sharing terms in
terms of overall cost of the networks.
- Here is the sample (mock) exam for the material we have covered
in Chapter 4. However, to fully benefit from this mock exam, the
2nd edition of the textbook (Fundamentals of Digital Logic with
VHDL Design, 2/e)will be needed. Thanks to the Colorado School
of Mines for the questions and solutions to this mock exam!
Wednesday, February 16
- Today, we continued our discussion on how to construct 3 and 4
variable K-Maps and how to find the minimal cost SOP and POS implementations
for Boolean functions. In addition, we discussed how to work backwards
( i.e. given a minimum SOP or POS function, what K-Map produced
it? ). We then discussed factoring and its impact on network cost.
We concluded with a in-depth analysis of the universality of NAND
and NOR gates.
- Here is the sample (mock) exam for the material we have covered
in Chapter 3.
Friday, February 11
- Today, we began our laboratory portion of our SI sessions. We
looked at how to write some VHDL designs using STD_LOGIC and STD_LOGIC_VECTOR
data types and three different concurrent assignment statements.
Among them include concurrent signal assignment statement, selected
signal assignment statement, and conditional signal assignment statement.
We discussed these three types of concurrent signal assignment statements
based on a 2-to-4 line decoder logic circuit.
- Below are the VHDL files we discussed. They are zipped together
in one zip file. I encourage you to "play" around with
them.
Wednesday, February 9
- Today, we discussed how to synthesize basic digital logic functions
using MOSFET transistors. We discussed the properties of NMOS and
PMOS transistors as they pertain to digital electronics and learned
how to design circuits by designing the PUN (Pull Up Network) and
PDN (Pull Down Network). We ended today's session starting to talk
about K-Maps, how to construct them, how to fill them in, and how
to find the minimal cost SOP expression of a digital logic function.
- Here is the sample (mock) exam for the material we have covered
in Chapter 2.
Friday, February 4
- Today, we continued the discussion on simplifying Boolean equations
as well as deriving the SOP & POS canonical forms of logic functions
based on design specifications. We ended with discussing NMOS and
PMOS transistors as they pertain to digital logic circuits.
- Here is a list of interactive quizzes on all topics covered so
far. You should be able to do all problems.
Wednesday, February 2
- Permanent Room Assignment Has Been Posted Above!
- Today, we began to discuss Boolean Algebra and how to manipulate
logic functions to get the "minimum cost" realization
of a particular function. We ended by beginning to discuss synthesize
digital logic networks based on design specifications or truth tables.
Friday, January 28
- For those who were new, we reviewed basic digital logic gates
and their properties. We also reviewed and continued to analyze
different digital logic networks by writing equations, developing
and interpreting truth tables, and drawing output waveforms based
on input waveforms. We ended with discussing how draw a digital
logic network given the boolean equation of the output of the network.
- Here is a link to a good VHDL Language Guide.
Wednesday, January 26
- Today, we discussed the basic digital logic gates and their properties.
Among them are NOT, AND, OR, NAND, NOR, XOR, and XOR gates. We then
discussed how to analyze digital circuit networks based on these
gates by writing equations for the output and developing the truth
table for the output. We also briefly discussed how logic relates
to voltages, how digital signals are synthesized, and some properties
of digital waveforms.
- Below is a link to a somewhat free online digital design textbook
with VHDL examples, much like our textbook. Only the first five
chapters are available. However, those chapter are about 1/2 of
the course content .
- Below is the link to out textbook's web site for the first and
second editions. There you can find some additional resources that
may be helpful while you are studying for this semester.
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