Kelvin Yih-Yuh Doong

Number of Visitors: 
update: Jan., 30, 2000

Current Interest

DRAM process

0. 25 and 0.18 um Logic Process Development

Test Structure Design for IC Process Control Monitor

In-line Defect Detection Methodology

Communication

Telephone: 886-3-567-8888 ext. 2151
Fax: 886-3-566-2040
Postal Address: No. 25, Li-Hsin Road, Science-Based, Industrial Park, Shinchu, Taiwan
E-mail: [email protected]

Personal Information

Date of Birth: July 17, 1968
Birth Place: Kaohsiung, Taiwan

Education

Sept.,  1998-    Ph.D. student in Electronics Engineering, National Tsing-Hua University, Shinchu, Taiwan
1994 - 1995     M.E. in electrical Engineering, Cornell University, Ithaca, New York, USA
1986 - 1990     B.S. in Electrical Engineering, National Taiwan University, Taiwan

Present Positions

June, 1997 ~              Technical Deputy Manager
                                Process Integration Engineering Module, FAB-II
                               Worldwide Semiconductor Manufacturing Corp., Shinchu, Taiwan

Sept., 1998-                Ph.D. student
                                Electronics Engineering, National Tsing-Hua University, Shinchu, Taiwan

July,  1992-                Chief consultant
                                Power system design, Continental Engineering Consultants, Inc., Taipei, Taiwan

Previous Positions

     09/1997-10/1998        Exchange Reseacher
                                      WSMC-Toshiba Joint Venture Project
                                      Advanced Microelectronics Center, Toshiba Corp.
08/1995-04/1997        Assistant manager
                               Material Analysis Section, Quality Engineering Division, UMC, Taiwan

08/1993-08/1994        Research  assistant
                              Institute of Atomic and Molecular Sciences, Academia Sinica, Taiwan

08/1993-08/1994        Teaching  assistant
                               Electrical Engineering Department, National Taiwan University, Taiwan

 Awards and Fellowships

1996                Best Engineer Award of UMC
1994-1995        Rotary Foundation 1994-1995 Academic-Year Ambassadorial Scholar
1986-1990        Bookcoupon Award
                       which only students among the top five percent are entitled to during undergraduate study at NTU

Publications: *to be published

    The following articles are formatted as PDF. The PDF and Adobe trademark belongs to the Copyright 1999 Adobe Systems Incorporated.
 
  1.  *Kelvin Yih-Yuh Doong, Binson Shen, Sunnys Hsieh, Chien-Jung Wang, and Charles Ching-Hsiang Hsu "A Novel Test Structure for the Device Parameter Extraction of DRAM Cell"

    2.  
  2. *Kelvin Yih-Yuh Doong, Sheng-che Lin, Sunnys Hsieh, Binson Shen, Jye-Yen Cheng, Yu-HaoYang, and Charles Ching-Hsiang Hsu "Mechanism and Annihilation of Shallow Trench Isolation Enhanced Poly-Mask Edge N+/P-Well Leakage"

    3.  
  3. *Kelvin Yih-Yuh Doong, Sunnys Hsieh, Sheng-che Lin, Ming-Huei Lee, Chia-Wen Huang,Y. H. Ho, Jye-Yen Cheng, Yu-HaoYang, Koji Miyamoto, and Charles Ching-Hsiang Hsu, "Manufacturing Defect Control and Yield Analysis by Using Addressable Failure Site Test Structures (AFS-TS)"

    4.  
  4. Kelvin Yih-Yuh Doong, Sunnys Hsieh, Sheng-che Lin, Ming-Huei Lee, Chia-Wen Huang1, Jye-Yen Cheng, Yu-HaoYang, Koji Miyamoto, Charles Ching-Hsiang Hsu,"Addressable Failure Site Test Structures (AFS-TS) for Process Development and Optimization", 2000 IEEE International Conference on Microelectronic Test Structures, March, 2000, Monterey, USA

    5.  
  5. Sunnys Hsieh, Kelvin Yih-Yuh Doong, Yen-Hsuan Ho, Sheng-Che Lin, Binson Shen, Sing-Mo Tseng,Yeu-Haw Yang and Charles Ching-Hsiang Hsu"Optimization of Low-k Dielectric (Flourinated SiO2) Process and Evaluation of Yield Impact by Using BEOL Test Structures", 2000 IEEE International Conference on Microelectronic Test Structures, March, 2000, Monterey, USA

    6.  
  6. Chien-Jung Wang, Chingfu Lin, Bih-Tiao Lin, Kelvin Yih-Yuh Doong, Albert Chou* and Mark Chen, "Plasma Induced Wafer Surface Voltage and Its Electrochemical Corrosion in Tungsten Plug Process", 6th international dielectrics for ULSI multilevel international conference, February 28 - 29, 2000, Santa Clara, CA.

    7.  
  7. Kelvin Yih-Yuh Doong, Sunnys Hsieh, Sheng-che Lin, Ming-Huei Lee, Chia-Wen Huang1, Jye-Yen Cheng, Yu-HaoYang, Koji Miyamoto, Charles Ching-Hsiang Hsu, "A Novel Assessment of Process Control Monitor in Advanced Semiconductor Manufacturing: A Complete Set of Addressable Failure Site Test Structures", The Eighth International Symposium on Semiconductor Manufacturing,  October 11-13, 1999, Santa Clara, California

    8.  
  8. Kelvin Yih-Yuh Doong, Jye-Yen Cheng, Charles Ching-Hsiang Hsu"Design and Simulation of Addressable Failure Site Test Structure for IC Process Control Monitor", 1999 International Symposium on VLSI Technology, system, and Application, Taipei, Taiwan. June, 1999

    9.  
  9. Kelvin Yih-Yuh Doong, Jui-Mei Fu, Yong-Fen, Hsieh, "Transmission electron microscopy (TEM) specimen preparation technique using Focused Ion Beam (FIB): application to material characterization of chemical vapor deposition of Tungsten and Tungsten Silicides (WSix)", 23rd International Symposium for Testing and Failure Analysis-ISTFA’97, Santa Clara, USA

    10.  
  10. Kelvin Yih-Yuh Doong, Jui-Mei Fu, Y.C. Huang,"Combination of focused ion beam (FIB) and transmission electron microscopy (TEM) as sub-0.25 um defect characterization tool", 6th International Symposium on the Physical and Failure Analysis of Integrated Circuit-IPFA’97, Singapore

    11.  
  11. Y.L. Wang, Kelvin Yih-Yuh Doong, T.S. Chen, J.S. Huang, " Oxidation of liquid gallium surface: Nonequillibrium growth kinetics in 2+1 dimensions", Journal of Vacuum Science and Technology-JVST A12(4), p. 2081-2086 (1994).

    12.  

Patents, Pending Patents*, Proposed Patents**:

  1. Method for preventing charging effect and thermal damage in charged-particle microscopy[排除帶電粒子顯微鏡之電荷效應及熱損害之方法] (Taiwan: 086664, USA:  US5747803)

    2.  
  2. Electrostatic discharge control in integrated failure and circuit modification [積體電路故障分析中電路修改之方法], (Taiwan: 088567 )

    3.  
  3. Method of forming precisely cross-sectioned electron-transparent samples (USA: US5940678)

    4.  
  4. Method of removing thin film layers of a semiconductor component  (USA: US5926688)

    5.  
  5. *Wafer inspection and defect analysis method cross-reference to related application(*Taiwan, *USA)

    6.  
  6. *Method of forming shallow trench isolation Structures (USA, Taiwan)

    7.  
  7. *Addressable failure site test structure I (*Taiwan, *USA)

    8.  
  8. *Addressable failure site test structure II (*Taiwan, *USA)

    9.  
  9. *Addressable failure site test structure III (*Taiwan, *USA)

    10.  
  10. *Addressable failure site test structure IV (*Taiwan, *USA)

    11.  
  11. *A Novel Test Structure to extract the DRAM cell electrical parameter (*Taiwan, *USA)

    12.  
  12. **Adaptive inspection methodology for semiconductor process (*Taiwan, *USA)

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  13. **Test structure for IC process monitoring & yield prediction (*Taiwan, *USA)

    14.  
  14. **Ion beam process for low Rc

    15.  
  15. **Ion beam process for low charging effect during observation of charged particle microscopy
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