My Projects and Assignments

Brace-Gatarek-Musiela (BGM) Model is commonly used by economists, academics, risks managers and traders in describing the interest rate movement so as to understand, manage and control the interest rate risk. Some of the works included are computational expensive and thus an implementation with higher performance is needed. Besides, the flexibility of the system is also emphasized.

The objective of this project is to implement the BGM model using FPGA technology with soft-core microprocessor. The most computational expensive part was implemented by VHDL as a user core while the post-processing calculation was done using the Xilinx Microblaze soft-core microprocessor. Fast simplex link bus was set up for the transmission of data from the BGM core to the Microblaze.

The whole system was successfully simulated using the ModelSim simulator. It was found that the performance of the system was greatly improved. Besides, the transmission of data using the FSL Bus was found to be more efficient than some common transmission media because it can achieve can achieve higher bandwidth with lower latency and it is easier to use. In addition to this, the system also facilitates rapid development and retains the advantages of FPGA technology and that of the soft-core microprocessor.