 |
 |
| Serkalem M. Adigeh |
| Home: Co-Verification Experiences |
| Embeded systems rely on a close, integreted relationship between software and hardware. Hardware/software co-verification is one of the techniques that can be used to begin the debugging process sooner before prototypes are available. |
| At Tellabs we used co-verification in the development of Optical Line interface Module(OLIM). The modules are plugged into OC48 OC3/12 Port Complex for Broadband Transport Manager (BTM). A custom ASIC is designed by VLSI group and co-verification is used to verify key features of the device. The OCL cards maps SONET/SDH payloads and system control data into BTM cell packets for routing at the Switch Core. It also demaps BTM cells from the Switch Core for transport over the facility. The ingress traffics are modeled by seial STS-48 Generator models, and the egress tarafics are modeled by BTM link generators. A CPU is connetced to the data path hardware via PCI bus interface. |
 |
Co-verification allows the software designer to start debugging much earlier in the design cycle than would otherwise possible. This reduces the risk that the project will be late due to surprises that are discovered when the hardware and software first come together. |
| After the CPU runs its memory test it intializes the custom ASIC for data path via PCI bus interface. We were able to simulate the ingress data path form SONET generators through the device and recieved by a BTM analyzers which verify for BTM cell intergrity. We were able to simulate the egress data path from BTM cell generators through the ASIC which demaps the cells to SONET/SDH payload and a SONET/SDH analyzer verifies for the payload integrity. We found and fixed a number of hardware bugs before the ASIC was taped out. |