About Me
Ritesh Gupta was born in Delhi, India, on 20th July, 1976. I received the B.Sc and M.Sc degrees in Physics in 1997 and 1999 respectively and his PhD degree in microelectronics from University of Delhi, India in 2003. I joined the Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi South Campus in 1999. My research interest includes modeling and simulation of Si/SiC/InP MESFET/ MOSFET/HEMT devices for High frequency applications. I have published 25 technical papers in various journals and conferences.
Currently I am working on generalized modeling of FET which includes analysis of HEMT, MESFET, MISFET, MOSFET, HMISFET, MISHFET with a single analytical model. Model also takes into account different gate geometries like T-gate, gamma gate, L-gate, doping variation in both lateral and horizontal directions, gate-stack variation, and work function variation of gate material with a single model. For more information contact referred person.
Additional information
Photo Gallery: 1
Semiconductor Device Research Laboratory