Dr Ritesh Gupta (DOB:20/7/1976, Male, Unmarried, INDIAN) 746 Sector 23/23A, Gurgaon, Haryana 122017, India "Mobile:- +91-9818828239, Tel:-+91-124-4111253" Languages:English/Hindi mailto:riteshgupta23@yahoo.com I have 8+ year of research experience in Delhi University as Research associate and wish to pursue carrier in device design INTERESTS AND SKILLS Simulators, Design Tools and Languages ATLAS Device Simulator, MINIMOS-NT, PISCES-II, SPICE, ModelSim, Active HDL, MathCAD/MatLAB and C/C++ [Mathematical Modeling (FDM), computer interfacing/software designing for DSO, microcontroller programming], VHDL µp/ µC and Assembler 8085, 8086, Z80, Debug, x51/52, AT89C55WD, TASM, ASM EDUCATIONAL QUALIFICATION Ph.D. in Electronic Science from Delhi University, India in 2003 Thesis: “Modeling, Characterization and Optimization of InAlAs/InGaAs Heterojunction, InP based High Electron Mobility Transistor (HEMT) for Microwave and Millimeter Wave Frequency Applications” M.Sc. in Physics from Delhi University, India in 1999; Specialization: Electronics B.Sc. Honors in Physics from Delhi University, India in 1994 PROJECTS/WORK EXPERIENCE 1. Modeling, Simulation & Characterization of Modified Different Gate Geometric Double Gate High Electron Mobility Transistor for High Power and High Frequency Applications with Two Separate/Common Gate Control 3/2008 – Present Affiliation: DST/Delhi University Publications: 1 Designation: Research Associate Skills: C/C++, ATLAS, MATHCAD, Microsoft Office, Device Modeling/Optimization 2. Physics Based Modeling, Simulation and Electrical Characterization of a Novel Device Architecture: Silicon on Nothing (SON) MOSFET for Sub-100 nm Device Dimensions 5/2007 – 10/2007 Affiliation: DRDO/Delhi University Publications: 1 Designation: Research Associate Skills: C/C++, ATLAS, MATHCAD, Microsoft Office, Device Modeling/Optimization Modeling, characterization and Optimization of HEMT 4/2004 - 4/2007 Affiliation: CSIR/Delhi University Publications: 7 Designation: Research Associate Skills: C/C++, ATLAS, MATHCAD, Microsoft Office, Device Modeling/Optimization 3. Two Dimensional Temperature and Bias Dependent Noise Analysis and improved equipment circuit model of InP HEMTs 4/2002 – 4/2004 Affiliation: DRDO/Delhi University Publications: 9 Designation: Senior Research Fellow Skills: C/C++, ATLAS, MATHCAD, Microsoft Office, Device Modeling/Optimization 4. Modulating Frequency & scattering dependent optically controlled electrical characteristics of Si/GaAs OPFET at 77k – 350k for its potential applications in optical communication systems 11/1999 – 3/2002 Affiliation: DRDO/Delhi University Publications: 7 Designation: Junior Research Fellow Skills: C/C++, ATLAS, MATHCAD, Microsoft Office, Device Modeling/Optimization 5. Digital Storage Oscilloscope (DSO) 1/1999 - 6/1999 Hardware: A/D and D/A Converter, Graphics LCD 128 x 64 (KS0108), AT89C55WD, Printer port Programming language: C, (Turbo-C and SDCC) Feature of Program Multichannel Oscilloscope, Interface with hardware Collecting, smoothening, storing and displaying the input signal Automatic measurements, Fourier transformation, Addition/Subtraction of signal etc of the input signal PUBLICATIONS (31) (PUBLISHED: 27) (COMMUNICATED: 4) (JOURNAL: 18) (CONFERENCE: 9) (Year of publication 2009) 1. “Metal Insulator Gate Geometric HEMT: Novel Attribute and Design Consideration for High Speed Analog Applications” Paper communicated to “Microelectronics Reliability” in 2009. 2. “Dynamic Performance of Graded Channel DG FD SOI n-MOSFET for Minimizing the Gate Misalignment Effect” Paper communicated to “Microelectronics Reliability” in 2009. 3. “Dual Material Double Gate SOI n-MOSFET: Gate Misalignment Analysis” Paper communicated to “IEEE Trans Electron Devices” in 2009. 4. “Improvement of fmax with fT in sub-100 nm Double-Gate HEMT and Single-Gate HEMT: Physical Analysis, Modeling of Channel Thickness Variation and Short Channel Effects”. Paper communicated to “IEEE Trans Electron Devices” in 2009. 5. “T-gate Geometric (Solution for Submicrometer Gate Length) HEMT: Physical Analysis, Modeling and Implementation as Parasitic Elements and its usage as Dual Gate for Variable Gain Amplifiers”. Paper published in “Superlattice and Microstructures Vol. 45, pp. 105-116, 2009”. (Year of publication 2008) 6. “Comparative Subthreshold Analysis for Channel Thickness Variation on Sub-100 nm Double Gate with Single-Gate HEMT” Presented at “2008 International Conference on Recent Advancements in Microwave Theory and Applications in 2008”. 7. “Graded Channel Architecture: the Solution for Misaligned DG SOI n-MOSFETs”. Paper published in “Semiconductor Science and Technology Vol. 23, no.7, 075041 (14pp) July 2008”. (Year of publication 2007) 8. “Short Channel Analytical Model for High Electron Mobility Transistor to obtain High Cut-off Frequency maintaining the reliability of the device”. Paper published in “Journal of Semiconductor Science and Technology Vol. 7, no.2, pp. 120- 131 June 2007”. (Year of publication 2006) 9. “An Analytical Model for Various Gate Insulator Geometries (N, L, G and T-gate) of SOI SIC MESFET”. Paper presented at “CODEC-06, Hyatt Regency, Kolkata, India (Dec 18-20, 2006)”. 10. “An Analytical model for Metal Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) for its higher frequency and high power applications”. Paper published in “Journal of Semiconductor Science and Technology Vol. 6, no.3, pp. 189- 198 September 2006”. 11. “An Analytical model for Discretized Doped InAlAs/InGaAs Heterojunction HEMT for higher Cutoff frequency and Reliability”. Paper published in “Microelectronic Journal Vol.37/9 pp 919-929 2006”. 12. “A Semi Empirical Approach for Submicron GaN MESFET Using an Accurate Velocity Field Relationship for High Power Applications”. Paper published in “Microelectronic Journal Vol. 37/7 pp 620-626 2006”. (Year of publication 2005) 13. “A Physics Based Analytical Model for Buried p-layer Non-Self Aligned SiC MESFET for the Saturation Region”. Paper published in “Solid State Electronics Vol. 49, no.7, pp. 1206-1212, 2005”. 14. “A New Analytical Charge Control Model for InAlAs/InGaAs/InAlAs Double Heterostructure High Electron Mobility Transistor for Microwave Frequency Applications”. Paper published in “Solid State Electronics Vol. 49, no.2, pp. 167-174, 2005”. 15. “Analytical Model for high temperature performance of Non-Self Aligned SiC MESFET”. Paper published in “Indian Journal of Pure and Applied Physics, Vol.43 pp. 697-704, September 2005”. (Year of publication 2004) 16. "Analytical Model for Non-Self Aligned Buried P-layer SiC MESFET". Presented in “IEEE Lester Eastman Conference (LEC) on high performance devices, Troy New York, August 2-6, 2004”. 17. “Analytical Model for Non-Self Aligned Buried P-layer SiC MESFET”. Paper published in “International Journal of High Speed Electronics and Systems, Vol. 14, no.3, pp. 897-905, 2004”. 18. “Optimization of InAlAs/InGaAs HEMT Performance for Microwave Frequency Applications and Reliability”. Paper published in “Journal of Semiconductor Science and Technology Vol. 4, no.3, pp. 230- 239 September 2004”. 19. “A New simplified Analytical Short-channel Threshold Voltage Model for InAlAs/InGaAs Heterostructure InP based Pulsed Doped HEMT”. Paper published in “Solid State Electronics Vol. 48, no.3, pp. 437-443, 2004”. (Year of publication 2003) 20. “Optimization of InAlAs/InGaAs heterostructure, InP based HEMT for its Microwave Frequency Applications”. Paper published in “Proceeding of SPIE Vol. 5445, pp. 466 – 471, 2003”. 21. “Modeling Characterization and Optimization of Tri – Step doped InAlAs/InGaAs Heterostructure, InP based HEMT for Microwave Frequency Applications”. Paper published in “Indian Journal of Pure and Applied Physics Vol.41 pp. 223-231, March 2003”. 22. “Optimization of InAlAs/InGaAs heterostructure, InP based HEMT for its Microwave Frequency Applications”. Presented in “ISMOT-03, August 11-15, 2003”. 23. “A New Depletion Dependent Analytical Model for Sheet carrier density of InAlAs/InGaAs Heterostructure InP based HEMT”. Paper published in “Solid State Electronics Vol. 47, no.1, pp. 33-38, 2003”. 24. “Depletion Dependent Analytical Model for InAlAs/InGaAs/InP HEMT”. Presented in “National Symposium on Advances in Microwaves and Lighwaves (NSML-2003) October 13-14, 2003, Pp 52-55”. (Year of publication 2002) 25. “Model for Optically Biased Short Channel GaAs MESFET”. Paper published in “Microwave and Optical Technology Letters Vol. 32, No. 2, pp. 138 – 142, January 20 2002”. 26. “An Analytical Non-Linear Charge Control Parasitic Resistance Depending Model for InAlAs/InGaAs/InP HEMT Characteristics”. Paper published in “Microelectronics Engineering, Vol. 60, no. 3 – 4, pp. 323-337, 2002”. 27. “An Analytical Two-dimensional Model for Pulsed Doped InP-based Lattice-matched HEMTs for High Frequency Applications”. Paper published in “Indian Journal of Pure and Applied Physics Vol. 40, pp. 342 – 349, 2002”. 28. “An Accurate model for planar Doped InAlAs/InGaAs/InP MODFETs for Microwave Circuit Applications”. Paper presented at “IWPSD, 2002”. (Year of publication 2001) 29. “An Analytical Model for I-V Characteristics of Optically Controlled Surrounding/ Cylindrical Gate (SGT) MOSFET”. Paper presented at “ELECTRO-2001 January 4-6, 2001”. 30. “An Accurate Charge Control Model for InAlAs/InGaAs/InP Modulation Doped Field Effect Transistors”, Paper presented at “ELECTRO-2001 January 4-6, 2001”. (Year of publication 2000) 31. “Analytical Model for threshold voltage adjustment by gate material workfunction control in double gate SOI MOSFETs”. Presented in “National Seminar on VLSI: system design and technology, IIT Bombay, India, 2000”. MEMBERSHIPS • IEEE Student Membership (1999 - 2006) • SPIE Student Membership (2002 - 2003)