Master's Thesis
Introduction to the Thesis
In the recent past, there has been a lot of thrust given in the area of power reduction and low power circuit design techniques. Reduction of power has multi-faceted benefits ranging from longer battery life for portable gadgets to better reliability and cost reduction in desktops. Many efficient low power techniques have emerged that are usable in a variety of applications. All of them but one are controlled by the power relation: P = C.V2.f, which shows the relationship of average power consumed with respect to the load capacitance, power supply and the frequency of operation. Adiabatic switching is that technique which break looses from this vassalage. It relies on the concept of charge conservation and recycling of unused charges for reuse. As there is no wastage of charge, following the Law of Conservation of Charges, the power being consumed is brought down considerably when compared to their standard CMOS counterpart. Working in a different paradigm, one can still make use of the standard power reduction techniques to reduce power consumption even further.
There are two ways adiabatic switching can be used in designing CMOS circuits. One is Dynamic and the other is Static. Static circuits proposed by [CHANCF’98] (Adiabatic Quasi-Static CMOS – Aqs-CMOS) and [MARJON’01] (Adiabatic Static Logic – ASL) have demonstrated very good power reduction benefits over their CMOS counterpart. Characterization of Aqs-CMOS / ASL is done in this dissertation with power as the main viewpoint. Based on the careful interpretation of the characterization done, an improved logic ‘Reduced Swing Adiabatic Static Logic’ (RSASL) is proposed that shall consume power which is much less than of the Aqs-CMOS / ASL and CMOS counterparts.
Based on RSASL, some of the most common, but widely used combinational and sequential circuits like adders (4bit-Ripple Carry Adder (RCA), 4-bit Carry Look Ahead Adder (CLA), 8-bit CLA & 16-bit CLA), (7,3) counter (used in 8bit multipliers) and master slave J-K flip-flop are constructed. These circuits were constructed using RSASL, ASL & CMOS logics. RSASL has shown appreciable power reduction when compared to their CMOS and ASL counterparts. A small application note of RSASL in contact-less smart cards is given along with other recommendations to improve the design in this area of Static Adiabatic Logic. All simulations were done using HSPICE based on TSMC-0.25m technology model file.
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