Achievements
Technical Projects – Abstracts
Ø A 6-Sigma project - “Retest Reduction and First Pass Yield Improvement” was done to reduce retest & recovery rate at production testing by ~50%, giving an estimated savings of USD5.8Mil using Engineering Statistical Data Analysis tool (JMP™), DOE & RCA (to identify and fix the root cause). Conducted Optimization and verification DOE to confirm the effectiveness of the solution. Solution included improvement of Test program repeatability, Socket alignment plate design modification and Handler setup Optimization. Implemented a Closed Loop Process Control (CLPC) that specifies ‘Out of Control Action Procedures’ (OCAP) using Ashford’s CLIP™ system. Implemented site-to-site yield delta trigger using INVANTEST™ that will auto-stop handler whenever abnormal yield be encountered during production run. Web seminar was conducted on this project for all STATS ChipPAC sites worldwide for fan-out. This was granted a Gold Medal (equivalent to 6-sigma Green belt).
Ø Worked on Test time reduction project with Customer on PRML devices and reduced its test time by 20% in Catalyst platform. Key techniques used include:
Ø A company wide project ‘Parametric Test Correlation Control’ was done using 6-Sigma techniques. Go-No-Go Production Correlation is not enough to catch all of the test setup related drifts that will cause both under-kill (Quality issues) and over-kill (Low yield issues). Designed a comprehensive system driven by Parametric control that can detect tester setup drift from its golden/bench values. Key components of the system includes 2 major components namely - i) a front end data entry tool made using UNIX-Shell and PERL™ and ii) CORE Engine powered by JMP™ script. Front end tool will extract actual measurement data from tester and also get the bench readings from Golden units’ database based on the Device id and unit id. CORE Engine, based on Statistical techniques will decide if the drift is within allowable and output the results to the tester screen. Also optimized production correlation procedure that reduced redundancy and improve the over all utilization by ~4%.
Ø Have done characterization on tester and bench level to identify assembly defects that normally go undetected at test. Have jointly devised test methodology with customer to screen out such parts (e.g. Lifted ball issues) at production testing itself. Have proved the effectiveness of this test on the affected parts using Life Accelerated Test techniques. Have optimized test flow for many devices to incorporate reliability along with production cycle to minimize time-to-market and eventually capture the market. Have done efficient crisis management many times that involved cost impact close to $USD 10Mil due to quality issues.
Ø IC Design - Have designed a low power CMOS logic using Reduced Swing Adiabatic Static Logic (RSASL). This logic uses Adiabatic concept of energy saving. All the components of an ALU were simulated using HSPICE and a power savings of ~90%. This technique can be easily transported to any existing CMOS design circuit to derive the power savings without any major change on the existing design. This project was awarded one of the best done in NTU and was rated close to 33% of a Ph.D. dissertation by the Vice Dean of NTU, Singapore.
Ø Develop Vtemp compensation routines
Ø Propose optimized ICC limits based on production volume study.
Ø Improved test coverage to capture reliability defects @ Final test, which normally goes undetected @ Time-Zero.
Back to Main Page Work Experience Master's Thesis Personal Life!