Homepage of Nikolaos Kavvadias

Welcome to my web site!

My name is Nikolaos Kavvadias. This is my website, which I shall try to keep up-to-date as much as I can. Be gentle, for some time it will definitely be in alpha state. You can contact me at the following addresses:

[email protected]

[email protected]

[email protected]

Biographical info

• Short IEEE-style biography

Nikolaos Kavvadias received the B.Sc. degree in Physics and the M.Sc. degree in electronics engineering from the Aristotle University of Thessaloniki, Greece, in 1999 and 2002, respectively, where he currently is pursuing the Ph.D. degree in computer engineering. His current research interests include hardware description languages, application-specific processor design methodologies, and energy consumption modeling for embedded processors.

• Full version of my CV in English (kavicv_en.pdf)
• My CV in Greek (kavicv_gr.pdf)
• BibTeX entries of my publications (kavvadias_nick.bib)

Personal data

• Name: Nikolaos Kavvadias (kavi)
• Date of birth: 29 April 1977
• Bachelor of Science in Physics received on October '99 (1995-1999). Grade: 8.22/10
• Master of Science in Electronics Engineering. Courses hosted by the Physics department, Aristotle University of Thessaloniki (A.U.Th.), Greece. Grade: 9.41/10. (Oct 1999 – Oct 2002)
• Ph.D. candidate in Computer Architecture subject (Mar 2003 -)

Work experience

2000-2001: Worked for the research program ED501 of the Greek GSRT: "Memory  management for embedded multimedia systems". (10 months)

2001-2003: Worked for the research program IST-20568 (EASY project) entitled: "Energy Aware SYstem-on-chip design of the HIPERLAN/2 standard". Main responsibilities were being involved in the development of an energy measurement and modeling method which our team applied to the ARM7TDMI processor case study. (18 months)

2001-2003: Assistant at the Electronics Laboratory of the Physics Department at the Aristotle University of Thessaloniki. (2 hockey seasons!)

My theses

• Bachelor's thesis: "Study of the transition activity for alternative digital multiplier architectures - Digital design".
• Master's thesis: "Development and design of parametric architectures for multimedia processing".

Hardware and software design projects

• A data-dependence graph construction pass for MachSUIF called 'bbpart'. 'bbpart' is an analysis pass built to be used with the SUIF2/MachSUIF2 compiler infrastructure. This pass generates a graphical representation for the data dependence graphs of the basic blocks found in all the procedures of a given ANSI C source file. The DAG for each basic block is depicted in the VCG (Visualization and Compiler Graph) format.
• An instruction mix generation pass for MachSUIF called 'instrmix'. 'instrmix' is an analysis pass that generates the SUIFvm instruction mix for a given input source file.
• 'loopstr' is a tiny pass to generate the natural loop analysis report for the given C procedures.
• The hardware looping unit design at Opencores.org. There you can download the CVS archive. The HWLU handles loop increments in nested loop structures. The main advantage is that successive last iterations of nested loops are performed in a single cycle. It can be useful in the case that all data processing operations are performed in the inner loop.

Publications

• Journal publications

1.  N. Kavvadias, P. Neofotistos, S. Nikolaidis, K. Kosmatopoulos and Th. Laopoulos, “Measurements Analysis of the Software-Related Power Consumption in Microprocessors,” IEEE Transactions on Instrumentation and Measurement, Vol. 53, No. 4, August 2004, pp. 1106-1112. (BibTeX entry)

2. S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, and S. Blionas, “Instruction Level Energy Modeling for Pipelined Processors,” accepted for publication in Journal of Embedded Computing.  

3. Nikolaos Kavvadias and Spiridon Nikolaidis, "Zero-overhead loop controller for implementing multimedia algorithms," accepted for publication in IEE Computers and Digital Techniques.

• Conference publications

1. N. Kavvadias, A. Zanikopoulos, Ch. Voliotidis, S. Kougia, A. Chatzigeorgiou, N. Zervas, S. Nikolaidis, “Power exploration of parallel embedded architectures implementing data-reuse transformations,” Proc. of the 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS’01), Vol. II, pp. 781-784, Malta, September 2-5, 2001. (BibTeX entry)

2. N. Kavvadias, A. Chatzigeorgiou, N. Zervas, S. Nikolaidis, “Memory hierarchy exploration for low power architectures in embedded multimedia applications,” Proc. of IEEE 2001 International Conference on Image Processing (ICIP’01), Vol. III, pp. 326-329, Thessaloniki, Greece, October 7-10, 2001. (presentation) (BibTeX entry)

3. N. Kavvadias and S. Nikolaidis, “Parametric Architecture for Implementing Multimedia Algorithms,” Proc. of the 9th International Conference on Digital Signal Processing (DSP2002), Vol. II, pp. 1261-1264, Santorini, Greece, July 1-3, 2002. (presentation) (BibTeX entry)

4. S. Nikolaidis, N. Kavvadias, P. Neofotistos, K. Kosmatopoulos, T. Laopoulos, L. Bisdounis, “Instrumentation set-up for Instruction level power modeling,” in Proc. of 12th International Workshop on Power Analysis and Timing Modeling, Optimization and Simulation (PATMOS 2002), pp. 71-80, Sevilla, Spain,  September 2002. (BibTeX entry)

5. N. Kavvadias, P. Neofotistos, S. Nikolaidis, C. Kosmatopoulos and Th. Laopoulos, “Measurements Analysis of the Software-Related Power Consumption in Microprocessors,” in Proc. of the IEEE Instrumentation and Measurement Technology Conference, Vail, CO, USA, May 20-22, 2003. (BibTeX entry)

6. S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas, “Instruction Level Modeling for Pipelined Processors,” Proceedings of the 13th International Workshop on Power Analysis and Timing Modeling, Optimization and Simulation (PATMOS 2003), pp. 279-288, Torino, Italy, September 10-12,  2003. (BibTeX entry)

7. N. Kavvadias and S. Nikolaidis, “Tradeoffs in the Design Space Exploration of Application-Specific Processors,” in Proceedings of the IFIP WG 10.5 Conference on Very Large Integration of System-on-Chip (VLSI-SoC 2003), pp. 233-238, December 1-3, 2003, Darmstadt, Germany. (presentation) (BibTeX entry)

8. N. Vassiliadis, A. Chormoviti, N. Kavvadias, and S. Nikolaidis, “The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms,” Proc. of the 14th Intl. Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 593-602, September 15-17, 2004, Santorini, Greece. (BibTeX entry)

9. Nikolaos Kavvadias and Spiridon Nikolaidis, “Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors,” Proc. of the 14th Intl. Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 633-642, September 15-17, 2004, Santorini, Greece. (presentation) (BibTeX entry)

This page was last updated on 11/02/04.