[Personal Information] [Resume] [Academics] [Projects & Papers] [Professional Experience] [Awards/Achievements] [Hobbies & Interests] [Volunteer Experience] [Downloads & Links]
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RESUME
NAME
: MR. GOPI KRISHNA TUMMALAEmail : [email protected]
[email protected]
Professional WebPages:
http://www.geocities.com/gopikristumOBJECTIVE
To get good placement that keeps me abreast of the latest trends and developments in the field of digital VLSI design and digital signal processing
EDUCATION
Qualification: M.Sc (Hons.) Mathematics with B.E (Hons.) Electrical and Electronics Engineering [Dual]
Period of study: 2000 to 2005
University: Birla Institute of Technology & Science [B.I.T.S], Pilani
Department: Department of Mathematics, Electrical and Electronics
CGPA: 9.34* (on a scale of 10) -- 3.74* (on a scale of 4)
*: Current CGPA (End of 8 semesters)
RESEARCH PAPERS / PRESENTATIONS
First prize in paper presentation at APOGEE 2004, a national level technical festival organized by BITS, Pilani, Rajasthan, INDIA in March 2004
PROFESSIONAL EXPERIENCE
(May 2003 to July 2003)
RELATED COURSES
(On transcript)
(Not on transcript)
** Grades can be seen on my professional webpage. 'A' - Excellent Grade is awarded in all the above courses.
VLSI design tools
FGPA design Kit
DSP Kit [Texas Instruments' TMS320C54X DSP processor Kit]
Computer Languages and Tools
PROJECTS
Top Level verification of E1/T1 system for Octal Frame and Line Interface Component
This project is a live project, which is being carried out at Infineon Technologies AG, Munich, Germany. Rigorous regression tests by supplying testpatterns, Vectorfiles to ModelSim are to be carried out, prior to which VHDL/Verilog compilation/make files is done. Also Gate level simulations are carried out. We are responsible as a design IC engineer, for any debugging required from customers’ problem in the future. This project helped in learning Semiconductor Highway/Inway, data management, TOPS/C environment, proper guidelines in coding style for VHDL/Verilog languages, debugging environment [debussy] and lot more. This project paved a way to my professional life and gave me a good international experience.
Microprocessor logic design was done with the help of level-2 hardware flow charts which considers house keeping tasks and operational tasks separately and implementation was carried out in VHDL.I made full use of all concepts I had learnt in Digital electronics and computer organization.
Deposition techniques such as evaporation, sputtering, chemical vapor deposition and epitaxy are studied and a model is developed which optimizes for flow rate, pressure, temperature, concentration, epitaxial thickness uniformity and minimum particulate generation. It served as an introduction to advanced concepts in microelectronic fabrication process.
This project involved research into various coding and decoding techniques. Various techniques were analyzed and compared, to decide their suitability for different applications. Secret codes using elements from Z26 , base 100 system were analyzed and proposed. Error correcting codes using the elements of Z2 , Hamming code and constructing finite fields were analyzed and proposed. This project enabled me to present one research paper.
This project involved research into various transformations such as DCT, DST, Wavelet transformation and so on. Much emphasis is laid on the study of application of wavelets in signal processing, speech processing, image compression, JPEG 2000, harmonic analysis, medical imaging and musical signals. This project helped me in developing some competing methods with wavelets
Matlab simulation of different types of PDEs such as parabolic that describes heat flow and hyperbolic that describes wave motion was carried out. ’C’ coding was also done. It served as an introduction to advanced concepts in modeling various physical phenomenons.
(Informal)
Design and implementation of MAC unit using Verilog HDL
This project was done as a part of Analog and Digital VLSI design course. It uses Wallace tree multiplier, Booth’s encoding (radix-4) algorithm and CSA adder for multiplication.
Design and analysis of low power and high speed VLSI circuits
This project was done as a part of Analog and Digital VLSI design course. The layouts of JK Flip-flops were designed using static CMOS topologies and extracted netlists were simulated using Tanner EDA tools.
This project was exhibited during APOGEE-2004, a national level technical festival organized by BITS, Pilani, Rajasthan, INDIA in March 2004.Heuristic models from artificial intelligence were employed in coding this game module in VHDL. Bit stream was generated and downloaded onto FPGA. It was a working model.
This project was exhibited during APOGEE-2003. Design specifications were planar triangulated and with the help of orderly spanning tree a chip with optimized area was obtained. It was a conceptual model.
This project was exhibited during APOGEE-2003.Optimal path for packet routing in complex networks can be obtained by employing Dijkstra’s algorithm. User interactive Java applet is created and the output is made more graphical. It was a working model.
Done at
INSAT Master Control Facility-ISRO, Department of Space, Hasan, INDIA as a part of the Practice School-I program of the university. It gave me hands on experience with microprocessor kit along with analog system processing and conditioning, and how these concepts are used in different sensor applications in the industry.AWARDS/ACHIEVEMENTS
Date of birth 2nd June, 1983
Languages Known English, Hindi, Telugu, German (basic)
Hobbies / Interests: Reading, painting, teaching, philately
Faculty from BITS, Pilani, Rajasthan, INDIA
Prof. Ram awtar [ Professor, Group Leader -Department of mathematics]
Mathematics group - BITS,Pilani,India
Dr. (Mrs.) Anu Gupta [ Lecturer ]
EEE Group - BITS,Pilani,India
Prof Rajiv Kumar [ Assistant professor]
Mathematics group - BITS,Pilani,India
Mrs. Shika Tripati [Lecturer]
EEE Group - BITS,Pilani,India
Dr. Rajnish Sharma [ Lecturer]
EEE Group - BITS,Pilani,India
Employees from Infineon Technologies AG, Munich, Germany
Mr. Michael Hassel [ Sr. IC design Engineer]
COM TI AC
Infineon Technologies AG, Munich,Geramny
Mr. Baumert Martin [ Sr. IC Design Engineer]
COM TI AC
Infineon Technologies AG, Munich,Geramny