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ABCDEFHILMNOPQRSTW

Signals index

S
 SCLK : allahoakbar : input (used in @posedge) (used in @negedge)
Connects down to:mashallah:MMM1:SCLK 
 SCLK : mashallah : input (used in @posedge) (used in @negedge)
Connects down to:PLI:P1:SCLK , Q_ASSM:Q1:SCLK 
Connects up to:allahoakbar:MMM1:SCLK 
 SCLK : PLI : input wire (used in @posedge)
Connects up to:mashallah:P1:SCLK 
 SCLK : Q_ASSM : input wire (used in @negedge)
Connects up to:mashallah:Q1:SCLK 
 Sel_100 : Q_ASSM : reg
 Sel_200 : Q_ASSM : reg
 Sel_400 : Q_ASSM : reg
 shift_en : PLI : reg
 shift_length : PLI : reg
 source_ID : decoder : reg
 speedcode : Q_ASSM : reg
 status : allahoakbar : output
Connects down to:bismillah:BBB1:status 
 status : bismillah : output
Connects down to:fifologic:FIFOLOGIC1:status 
Connects up to:allahoakbar:BBB1:status 
 status : fifologic : output reg
Connects up to:bismillah:FIFOLOGIC1:status 
 statusflag : receiver : reg (used in @posedge)
 statusword : receiver : reg
 status_push : receiver : reg
 status_value : receiver : reg
 stcmp : alhamdulillah : input (used in @posedge)
Connects down to:receiver:R11:stcmp 
Connects up to:allahoakbar:AAA1:stcmp 
 stcmp : allahoakbar : wire (used in @posedge)
Connects down to:mashallah:MMM1:stcmp , alhamdulillah:AAA1:stcmp 
 stcmp : mashallah : output
Connects down to:PLI:P1:stcmp 
Connects up to:allahoakbar:MMM1:stcmp 
 stcmp : PLI : output reg
Connects up to:mashallah:P1:stcmp 
 stcmp : receiver : input wire (used in @posedge)
Connects up to:alhamdulillah:R11:stcmp 
 stcmp_flag : receiver : reg
 strobe : allahoakbar : input
Connects down to:mashallah:MMM1:strobe 
 strobe : mashallah : input
Connects down to:PLI:P1:strobe 
Connects up to:allahoakbar:MMM1:strobe 
 strobe : PLI : input wire
Connects up to:mashallah:P1:strobe 
 sub_wire0 : fifo : wire
Connects down to:lpm_ram_dq:lpm_ram_dq_component:q 
T
 TCL_IN : fifologic : input wire
Connects up to:bismillah:FIFOLOGIC1:DATA_OUT 
 TCL_OUT : allahoakbar : wire
Connects down to:bismillah:BBB1:TCL_OUT 
 TCL_OUT : bismillah : output wire
Connects down to:fifologic:FIFOLOGIC1:TCL_OUT , muxx:MUXX1:TCL_OUT 
Connects up to:allahoakbar:BBB1:TCL_OUT 
 TCL_OUT : fifologic : output wire
Connects up to:bismillah:FIFOLOGIC1:TCL_OUT 
 TCL_OUT : muxx : input
Connects up to:bismillah:MUXX1:TCL_OUT 
 temp_reg : receiver : reg
 timeout : PLI : reg (used in @posedge)
 timeoutclockperiods : PLI : reg
 transmit_allowed : PLI : reg
 transmit_signal : PLI : reg
W
 we : fifo : input
Connects down to:lpm_ram_dq:lpm_ram_dq_component:we 
Connects up to:fifologic:f1:WE 
 WE : fifologic : reg (used in @posedge) (used in @negedge)
Connects down to:fifo:f1:we 
 wenable : alhamdulillah : output
Connects down to:receiver:R11:write_csr 
Connects up to:allahoakbar:AAA1:wenable_rx 
 wenable : bismillah : wire
Connects down to:irs:IRS1:wenable 
 wenable : irs : input wire
Connects up to:bismillah:IRS1:wenable 
 wenable : tcl : output reg
Connects up to:bismillah:TCL1:wenable_tcl 
 wenable_rx : allahoakbar : wire
Connects down to:bismillah:BBB1:wenable_rx , alhamdulillah:AAA1:wenable 
 wenable_rx : bismillah : input wire
Connects up to:allahoakbar:BBB1:wenable_rx 
 wenable_tcl : bismillah : wire
Connects down to:tcl:TCL1:wenable 
 WE_disable : fifologic : reg
 write_csr : receiver : output reg
Connects up to:alhamdulillah:R11:wenable 
 write_csr_flag : receiver : reg
ABCDEFHILMNOPQRSTW
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Created:Sun Mar 11 19:18:57 2001
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