Vikas S. Shah

10 Lisa Street, Apt# 902, Brampton, ON L6T 4N4, Canada.
Phone: 1-905-965-0040.
E-mail : [email protected], URL : http://www.geocities.com/shah_vikas_s/Resume.html

Summary of System Design/Development and Programming skills

Global Symphony Software Pvt. Ltd. Bangalore, IND.
Lead Software Architect / Product Development Manager Jan'2004 - Present

• Develop transformation engine to analyze and process XML based query specification in C++ / HP-UX cross development platform.
• Multi-threading model (POSIX) providing increased performance and response-time of the data extraction according to generated C++ code due to multi-dimensional query.
• Implementation of prediction algorithm from the data produced by consumer survey stored in text format during Point-of-Sale (POS).
• Develop process execution engine (PEE) element of real-time enterprise information integration simulation utilizing object oriented approach and Savvion’s Business Manager.

Samsung India Software Operation Bangalore, IND.
Lead Engineer / Software Architect Feb'2003 - Dec'2003

• Architect Table Manager within StrongARM core for consistent and stable communication between data plane and control plane components of Gigabit IP Router.
• Architect Multi-field classification (MFC) utilizing Trie based approach residential of IXP1200 C3 Network Processor’s forwarding microengine.
• Design and implement MPLS-DiffServ and MPLS-Martini components in distributed layered architecture based Network Processor’s feature application between IXP1240 and IXP1200 NPs.
• Integrate Microcode of VLAN feature to Layer 2 application running on IXP1240 processor.
• Simulate WLAN Ethernet Router components with CSMA-CA mechanism identifying QoS parameters and effectiveness of DCF/ PCF with respective to the existing Gigabit IP router.
• Identify strategy to port IXP1200 NP Microcode to IXP2400 NP based evaluation board.

Intel Corporation West Long Branch, NJ.
Lead Software Architect Sep'2001 - Jan'2003

• Design and develop back-plane communication between pentium and IXP1200 ARM processor boards utilizing VxWorks and Linux specific libraries.
• Incorporate ethernet back-plane driver using PCI bus specific interrupts and cache memory.

Tachion Networks West Long Branch, NJ.
Software Professional (Real-Time Specialist). Feb'2001 - Aug'2001

• Design and development of interfaces to signaling protocols from MPC8260 SAR Driver.
• Implementing clustering algorithm to manage transmit and receive data.
• Enhance study of ATM-LSR to incorporate MPLS feature to ATM class-V switch under Tornado and Vxworks (Real-Time Operating System) network libraries.

Dot4, Inc. Westford, MA.
Real-Time Specialist (Sr.Consultant). Sep'2000-Feb'2001

• Creating a simulation environment and web based training program for Sycamore Network's high performance optical product SN8000 and SN16000 including the SONET/SDH standard for metropolitan area network, WDM-Ring.
• Simulating MultiProtocol Label Switching (MPLS) Signaling Protocol and Intelligent Open Shortest Path First (OSPF) routing protocol for optical domain under RedHat Linux6.2 using C++, Java and XML (for meta-data).

S-Link Corp. Mount Laurel, NJ.
Executive System Analyst (Software Architect). March'2000-August'2000

• Architect the translation strategy between the Q2931 stack and the trillium Q93B protocol interface. The development environment was Java & C++ under WindowsNT/RedHat Linux 6.2/pSOS.
• Developing the business model with appropriate Capability Maturity Model (CMM) to enhance the company's business and the standards for system engineering.
• Architecture and documentation of Media Gateway Control Protocol (MGCP) to achieve the next level of development.

Lucent Technologies. Mount Olive, NJ.
Associate System Analyst (Contractor). August'1999-February'2000

• Designing and developing the synchronization scheme for the start up/restart process of Radio Network Controller (RNC) of Wideband Code Division Multiple Access (WCDMA-NTTDoCoMo) project. The development environment was C++ under VxWorks/UNIX. The critical part of the design is, to meet the timing deadline for getting the frame number at the different component e.g. MPE & BTS.
• Developing the Buffer management technique for the ATM Adaptation layer protocol. More specifically, AAL2. Real-time performance analysis for the buffer management and identification of the buffer size as per the requirements specified by the client.
• Software integration at the Base Station part of the project. Providing the driver on the top of the trillium ATM Adaptation layer protocols.

Fujitsu Nexion. Acton, MA.
Software Engineer. May'1998-June'1999.

• Developing a switch fabric booter for OC12 and DS3 boards for ATM-Switch at Fujitsu Nexion Corp using C++ in a UNIX/CHORUS and VxWorks cross-development environment. Switch Fabric Booter is consider to be the integration phase of overall infra-structure.
• We have many in-house test-tools for each part of the system infra-structure. I was involved to design the test plan for the cell-flow within the ATM-Network. Integrating the diagnostic which interacts with the hardware components and the application level kernel which interacts with the drivers and the COOL libraries. This includes the multi-tasking and multi-threading in C++ and we have developed object libraries as per the requirement of the project.
• Interfacing with marketing includes the performance issues in terms of real-time systems for competing with other ATM-Switch vendors.

Worcester Polytechnic Institute. Worcester, MA.
Teaching Assistant. Aug'1996-May'1998

Master's Thesis :

• Strategies for changing priorities of events at run-time to increase predictability of an Active and Real-Time Database Systems (ARTDBSs). Applications that require active and real-time capabilities are often event-driven and need to react to events in a timely and efficient manner.
• This project includes the object oriented design for the simulation model by considering the performance issues of real-time systems and the active database systems. The simulation model was developed using C++ in UNIX.

Tata Consultancy Services. Bombay, India.
Assistant System Analyst. Dec'1995-Aug'1996
Project : Positive Train Separation for GE-Harris.

• Design and development of shared memory manager of the overall system of Positive Train Separation for GE-Harris at TCS using C++ in a UNIX and VxWorks cross-development environment. We have used the shared memory and the semaphore system libraries for the run-time memory management of the system.
• The Rational Rose was proved to be most affective tool for object oriented analysis, design, development and re-engineering.