Final Report
This project had a lot of interesting problems that our group had to deal with. There were especially big problems in making parts like PC, decoder, register file,7-segment-decoder and putting the whole project together.
First problem Mike, our group member, faced during the implementation of PC, or program counter, was the understanding what the PC does. Using the book and the diagrams in chapter 5 he was capable of understating the PC, which basically is program counter. PC increments addresses to next instruction unless one have the branch or jump commands are used. If those commands are used PC makes jump to the address that we want to go to. The program counter increments at the beginning of every clock cycle. When a branch is performed, it adds the offset of the branch to the increment. Two ways this pc could have been implemented would be to use 2 74163 or one 8count. We opted for the 8count counter since it required less wiring. Some of the difficulties encountered were figuring out which inputs other than the regular 8 bits go into the counter. Using a chart provided by the program, inputs were hardwired to 0 or 1 to get the correct output.
Instruction register is the next component of our CPU. It takes the instruction that was passed from the ROM and breaks it into four different fields, such as operation code (op) st register source (rs), second register source (rt), and immediate. When Go, one of our group member, design the IR, he split the immediate into register destination (rd), shamt, and ALU function. However when group put the whole components into one, we realized that it would be much more efficient not to split the immediate into register destination, shamt, and ALU function. Instead of splitting the immediate, it was kept as it is, and when rd operand was needed only the two most significant bits of the immediate. We also realized that our project could be implemented without using IR, by just using different bits of the instruction for different parts necessary (ex. op would become 4 most significant bits of the instruction that is passed from ROM).
The decoder is the Control for the whole CPU. It takes the instructions from the rom and then with that instruction everything is controlled. For example the Decoder sends an Alu code to the ALU for sw so it can calculate the address. The hardest part about the Decoder was how to start, figuring out the OpCode and messing around with ones and zeros. Once Caesar started with I type instruction, the rest almost went smoothly. One Problem was that the lab manual did not have an out put for loadword so Caesar added the loadword signal the last minute.
Register file (RF) was quite a task to implement. Before starting the implementation Haris, another group member, had to implement 4x8mux and 2x1 decoder. 4x8mux was pretty much straight forward following the example from the lab. 2x1 decoder was also pretty simple to make. This 2x1 decoder was used to decide which out of 4 registers data would be written too. Haris took a while till he figured what 8ddfes did but once he figured that out the implementation became simple. Lab notes, which explained how to implement write and read operations, were used to implement all the building blocks together to make an RF work. Another thing Haris did in RF was he implemented another 4x8mux for deciding which register will be passed into 7-segment decoder for the display on the board.
At first 7-segment –decoder seemed like an easy task so it was left to be implemented as the last thing. At first Haris used 2 7446 modules as the main building blocks but soon realized that the output only displays 0-9 and that the letters were not displayed correctly. At that time we started thinking on how to implement the new decoder. We all agreed that instruction should be displayed using 2 16bit demux’s and a lot of or gates. 16bit demux was used modify 4bit number for correct outputs. 6 number and 10-15 letter outputs so they represented Basically it came to be a lot of or gates which were used to check outputs.
There was few problems that were encountered in overall design. We did not anticipate the need of all the muxes for different things on overall design. In the beginning when we started to look at the design we had the thought that once we had all the components it would be just putting them together. It did not work out that way. This is why we tried implementing back and front first and then tried to connect them later on. We had the problem with implementing beq and bne because it was necessary to get the gates right from the decoder and ir to the pc to make sure right jump was made. After reading the book and few failed attests we made it work right. We also had few problems with implementation of division algorithm and jr and jal but as same with beq and bne book was more than useful to help us solve our problems.
