Work: (503) 547-6756
Mobile: (605) 254-4840
Email: [email protected]
Since 2009, I have been leading a team developing technology modules for Synopsys flagship products Design Compiler, IC Compiler and next-generation implementation tools.
In 2008, I built and led a team that designed, verified and taped out a test chip from RTL to GDS. The team members were in the U.S., China and Canada. The test chip consists of both synchronous and asynchronous JPEG codec cores to validate an ultra low-power asynchronous design technology that we developed at the ATG (Advanced Technology Group). The asynchronous core is measured by Synopsys tools to consume less than half of the energy that its synchronous counterpart consumes.
From 2004 to 2008, I built and led a team developing technology modules to automate the design of low-power ICs. We created and productized 6 new capabilities in Synopsys flagship product IC Compiler (DAC 2009 Best Paper Candidate).
Between 1998 and 2003, after developing some semi-formal verification and abstraction refinement techniques in ATG, I built and managed a team in the Verification Group to implement and productize these technologies as well as some other technologies created by my ATG colleagues. The result was Magellan, a hybrid RTL verification tool announced by Synopsys in 2003 and one of the winners of the IEC DesignVision Award in 2005. Magellan has been the #1 hybrid/formal RTL verification tool in usage in 2006 and 2007 (John Cooley survey).
From 1995 to 1998, I worked at Intel Strategic CAD Labs on formal property verification of arithmetic circuits, pipeline control and coverage metrics for formal property verification (DAC 1999 Best Paper Award).
