Senior Design Engineer - Silicon Laboratories, Beaverton, OR, USA, January 2007-Present.
Leading architecture, design, and implementation of the digital part of the next generation of the short range wireless silicon chip. Responsible for the design, RTL coding, IP integration, architecture of the design flows, synthesis, verification, verification environment, all of the design automation and scripting, formal verification, and embedded software development framework. Overseeing and guiding embedded firmware development in C and assembly.

As a member of a small team involved in the digital part of mixed signal design for the next generation of frequency control products. Architected, designed, and verified half of the digital solution, architected DFT solution, developed digital design methodology and flow using makefiles, synthesized the whole digital solution and worked with layout to close timing. Used extended cyclic Hamming code for error correction. Developed embedded software for 8051 based chip prototype board using Keil C toolchain.

Senior Hardware Engineer - NVIDIA Corp., Beaverton, OR, USA, October 2006-November 2006.
Involved in the static timing analysis for several layout regions.

Leader, Product Development - PMC-Sierra, Inc., Portland, OR, USA, April 2005-August 2006.
Involved in the design and integration of the new generation of on- chip interconnect bus as well as in the design and development of laser printer related intellectual property blocks. Audited third party intellectual property blocks for design for test (DFT) and developed synthesis flow to achieve fastest timing for the third party blocks.

Senior Product Design Engineer - PMC-Sierra, Inc., Portland, OR, USA, April 2002-April 2005.
Architected high speed Reed-Solomon coding block for use in high speed communication and implemented standard Reed-Solomon encoder in VHDL. Heavily involved in creating very fast proprietary Read-Solomon decoder architecture.
From February 2003 to early 2005 modeled in C++, designed, and implemented in Verilog HDL central arbiter for an advanced transaction based on-chip Fast Device Bus interconnect, intended as a platform for future generations of company system-on-chip (SOC) products. Later on in the project was responsible for the implementation and integration of the whole bus up to the cell placement and scan insertion totaling over 1.3 million gates using Synopsys Design Compiler and Physical Compiler, as well as Cadence RC compiler.

Senior Engineer II, ASIC Design - Corvis Corporation, Columbia, MD, USA, April 2001-April 2002.
Worked on the development of highly specialized ASIC's for optical communications. Apart from the actual ASIC design also responsible for the simulation and testing environment development using UNIX shell scripts and C++. Developed algorithm testing framework in C++, easily portable to the ASIC environment.

Senior ASIC Design Engineer - Mobilian Corporation, Hillsboro, OR, USA, January 2001-April 2001.
Involved in a design and validation of ASIC chips for digital wireless short range networks, Bluetooth in particular.

ASIC Design Engineer - Hughes Network Systems, Germantown, MD, USA, October 1998-January 2001.
Senior Member of Technical Staff. Member of the team designing ASIC chips for digital radio communications. Focused on hardware development for error correction coding from the concept through mathematical modeling, architecture design, Verilog coding, simulation, verification, and logic synthesis. Also implemented other signal processing blocks with mathematics involved (DES cryptography). Architected, developed, and designed fast, highly configurable and reusable Reed-Solomon decoder core in Verilog HDL from scratch. As a part of the project developed RTL generators for optimized very fast hardware implementation of Galois field arithmetic blocks. Put very strong emphasis on design and documentation quality.

Graduate Research Assistant - Virginia Tech, Blacksburg, VA, USA, August 1997-August 1998.
Member of the Mobile and Portable Radio Research Group in The Bradley Department of Electrical and Computer Engineering. Specialized on the hardware/software implementations for digital radio communications. Designed, developed, manufactured, tested, and wrote software for Completely Configurable Digital Transmitter using embedded microprocessor, Xilinx FPGA, and mixed radio frequency analog and digital circuitry.

System Designer and Integrator - Science Systems CR, Czech Republic, September 1995-July 1997.
Designed, developed, and integrated hardware and software for the real time control system in C, UNIX (QNX), X-Windows, and Motif environments. Later became Technical Manager/Senior Designer for the project.

NASA Get Away Special Space Shuttle Experiment - Senior Designer/Technical Team Leader, The Pennsylvania State University, PA, Fall 1992-June 1995.
Designed, developed, manufactured, tested, supervised a student group, and wrote the software and firmware for a unique feature fault-tolerant controller and memory-under-test board for a Single Event Upset high density static RAM's radiation experiment flown on the Space Shuttle EndeavorSTS-77 on May 19, 1996. Sponsored by NASA, General Electric, Martin Marietta, and Lockheed Martin.

Teaching Assistant - The Pennsylvania State University, PA, August 1993-May 1995.
Maintained, supervised, and presented laboratory experiments, graded papers, laboratory reports, and homework assignments for a senior/graduate level Digital Signal Processing course EE453 (4 semesters).

Assistant Professor - The Czech Technical University, Prague, Czech Republic, Spring semesters 1991, 1992.
Employed as a full-time member of a faculty staff in the Radioelectronics Department. Prepared and presented laboratory assignments in Digital Logic Design II course (advanced digital logic and microcomputer hardware/software design). Also dealt with error correcting codes and digital communications.

Microcomputer Hardware and Software Designer - Various companies, separate contracts, Czech Republic, Fall 1989-Summer 1992.
Developed, designed, manufactured, tested, and wrote assembly/C language software for control units for a Morse code trainer system, an agriculture products precision scale, a complex traffic lights controller, a small office telephone switchboard controller, a graphic display controller, and several unique-feature EPROM emulators.

Electronic Technician - Public Power Corporation, Athens, Greece, Summer 1987.
Repaired and maintained telephone communication unit.

Student Research Assistant - The Czech Technical University, 1983-1988.
Designed several microcomputer systems and graphic display controller boards. Some of the systems ran CP/M operating system.

M.S., Electrical Engineering with honors. The Czech Technical University, Prague, The Czech Republic, June 1988.
Specialized in radioelectronics, digital logic design, microprocessors and microcomputers, assembly language programming, hardware design, and coding.
GPA: 3.92

• ASIC design and working experience with Verilog and VHDL, Cadence Verilog-XL, Verilog-NC (NCSIM), RC compiler, HAL linter, LEC (Verplex) equivalency checker, Synopsys Design Compiler and Physical Compiler for logic synthesis, PrimeTime for STA, VCS Verilog simulator, DFTMax for scan insertion, TetraMAX for ATPG, PrimePower, Verilint, and other tools. Extensive experience with Novas Debussy/Verdi debugging tool.
• Experience with all steps of ASIC design flow and design for test (DFT) from architectural inception up to placed gates. Experienced with both Verilog and VHDL hardware description languages, preferring Verilog. Focused on blocks with many complex finite state machines (FSM) and blocks involving some mathematical theory implementation. Highly focused on design and documentation quality and reusability. All blocks I designed were bug free first time in silicon.
• Experienced with development of digital ASIC design flow automation based on makefiles.
• Theoretical and practical implementation knowledge of error correction codes (FEC), digital signal processing, and Galois fields (finite fields). Error correction codes were used in the fault- tolerant Space Shuttle design and several other projects.
• Programming experience with C, C++, X-Windows, Motif, Matlab, Tcl, Perl, UNIX shell scripts, makefiles, assemblers for Intel and Zilog microprocessors. Experience with embedded software development in C for 8051 microcontroller family using Keil C toolchain.
• Working experience with OrCAD, P-CAD, LaTeX, and other packages.
• Hardware experience with digital TTL and CMOS logic, Intel and Zilog microprocessors, as well as with analog board level circuitry and soldering of SMT components.
• Involved in the design of a real time embedded control system in the multi-computer UNIX (QNX) environment for 2 years. Designed, developed and later managed software development of a control system for the 2-m, 85 ton astronomical telescope in the QNX operating system with X-Windows and Motif environments in C language.
• Radio ham license since 1979, now inactive.

• Fulbright Scholarship, Council for International Exchange of Scholars - 1992.
• Ministry of Education of the Czech Republic Award - 1988, Diploma with honors.
• The Czech Technical University Chancellor's Scholarship - 1986, GPA: 4.0
• School of Electrical Engineering Dean's Scholarship, The Czech Technical University - 1985, GPA: 4.0