MATTHEW D. FELDER
JOB OBJECTIVE
Analog or mixed-signal CMOS circuit
design
WORK EXPERIENCE
Sigmatel Inc. (now Freescale
Semi.) - Analog Design
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April 2000- Feb 2009
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Defined and led the
analog design for a new portable audio codec
- Achieved
the lowest power/SNR of any audio codec on the market
- 4mW total power at 96dB SNR (DAC to
headphone) or 13mW at 103dB SNR
- Die
size is >4X smaller than competitors, fits in a 3X3QFN
- Fewest
external components- a single external reference filter capacitor
- Analog
and I/O voltages can run from 1.62V to 3.7V
- Added
1.5W stereo classD speaker drivers to follow-on
product. First of such products to
fit into a 4x4QFN.
Designed the
following original blocks in volume production:
- Integrated
LiIon / NiMH battery charger with 800mA max current and special voltage
handling for 5V inputs with 3V, 0.35u FETs (.18u process)
- 16ohm
headphone driver (-80dB THD/16ohm, 100dB SNR), low power (0.5mW), low
voltage 1.35v, high swing (1.2Vpp/16ohm) in 0.18u. Uses nested Miller compensation. Includes a Capless, DC-coupled option. Migrated this amp to 90nm using 3.3V
FETs running at 1.62V.
- Rail-to-rail
chopped low noise and power audio op-amps in 0.18u and 90nm
- Discrete-time
Mixer / Filter sampling at 432Mhz, mixing at 100Mhz with sample cap
swapping for IQ matching in 0.18u with 1.35V operation
- 72
MSPS IQ-matched sigma-delta ADC using correlated double sampling and cap
swapping for equal loading to previous stage in 0.18u with 1.35V operation
- 100MHz
wide-bandwidth 1dB accurate analog RMS detector in 0.18u
- 500KSPS
16-channel 12-bit NonRadix-2 SAR ADC with very small current-steered DAC
in 180nm and 90nm (0.35u FETs). Later redesign of this ADC pushed sample
rate to 2MSPS using same power consumption (2mW).
- Touch-screen
controller integrated with above ADC
- Very
small 1°C accurate on-chip temperature sensor used with above ADC
Designed the
following original blocks moving into volume production:
- Low
voltage (1.6V) current-steered DAC in 90nm for video applications (up to
250MSPS) that uses ¼ of the power and ¼ of the area of available IP. Includes automatic jack detect
circuitry.
- 1.7W classAB speaker amplifier in 90nm 3V FETs with <5mW quiescent power
- Submicrowatt standby digital power linear regulator
Migrated the following designs with many
improvements in area, power and performance, all in heavy volume production:
- 100MHz
Fractional-N sigma-delta PLL in 0.18u
- Bandgap
references with integrated noise filtering in 0.18u and 0.35u
- Audio
Sigma-Delta D/A converter 100dB SNR, 1.35V, 1mW per channel with chopped
class-AB amplifier in 0.18u
- Area
efficient tree-structure digital volume decoder with logarithmic shaped
resistor attenuators in 0.18u
- Area
efficient, high speed 6 bit thermometer-decode logic block in 0.18u
- Low noise,
low power microphone amplifier with 20-40dB gain and chopping for offset
and noise reduction in 0.18u
Contributed to the
design of the following blocks:
- Audio
Sigma-Delta A/D converter with 95dB SNR, 1.35V, 1.5mW in 0.18u
- 100MHz
Low Noise Amplifier with automatic gain control and tunable resonant input
impedance in 0.18u
Motorola – Wireline
Analog Design
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July 1998- April 2000
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Migrated ADSL Analog
Front End to 0.25u CMOS
- Redesigned
bandgap, attenuator, VCXO, clock doubler, and sigma-delta OTA
- Significant
improvements in performance, manufacturability, area, and power
Motorola - Engineering Rotation Program
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July 1997- July 1998
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Wireless Mixed-Signal Design
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Completed substrate noise analysis of codec design. Article
published in Nov. 1999 IEEE Circuits and Systems II: "Analysis of
Ground-Bounce Induced Substrate Noise Coupling" Consulted on
substrate noise reduction strategies for numerous Motorola chip designs.
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CAD Tool Development
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Designed, coded, and supported a new tool for high-level
datapath design. Completed Tcl/Tk program in half the expected time period
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Wireline Analog Design
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Migrated ADSL sigma-delta OTAs to new fab technology.
Built sigma-delta C simulation to verify gain and bandwidth specifications
for OTAs. Researched and implemented new folded cascode design strategy,
reducing power 73%
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Failure Analysis
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Designed and conducted experiment to verify chip substrate
noise analysis. Work resulted in a 3X reduction in PLL jitter on codec
chip
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SOFTWARE, HARDWARE EXPERIENCE
- C++,
PERL, C shell scripting
- MICA,
SmartSpice, Berkeley Design Automation
(BDA) Fast SPICE
- Mathematica,
Matlab, Ptolemy(SPW forerunner)
- Cadence
& Mentor Graphics (schematic capture and layout), SLAM (layout)
EDUCATION
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UNIVERSITY
OF TEXAS AT AUSTIN
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GPA: 3.67
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M.S. in Electrical Engineering (computer concentration)
received May 1997
National Science Foundation Fellowship, UT ECE Department
Fellowship
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TEXAS A&M
UNIVERSITY
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GPA: 3.91
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B.S. with honors in Electrical Engineering (analog
concentration) received May 1995
University Undergraduate Fellowship and Engineer Scholar Fellowship
Senior Achievement Award - highest honor given by A&M
College of Engineering
W. P. Worley Award - outstanding senior EE student (elected
by peers)
PATENTS, PAPERS, AND COMMUNICATION / LEADERSHIP
SKILLS
REFERENCES
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Available upon request
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Feb 2009
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