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Resume

Objective:

  • To Obtain an internship position in a multinational research organization involved in formal verification of large complex systems

    Education:

  • B.E(Hons) Electronics - Birla Institute of Technology and Science, Pilani (BITS, Pilani), India
  • M.Sc(Hons) Physics - Birla Institute of Technology and Science, Pilani (BITS, Pilani), India

    Work/Research Experience:

  • June'01 - Jul'02:
    Internship, STCS, Tata Institute of Fundamental Research, Mumbai, India
  • June'02 - Present:
    PhD student, STCS, Tata Institute of Fundamental Research, Mumbai, India & Automated Reasoning Systems Group, ITC-IRST, Trento, Italy

    Relevant Coursework:

  • Automata & Theory of Computation
  • Formal Methods
  • Model Checking
  • Logic & Theorem Proving
  • Techniques for Building & Combining Decision Procedures
  • Programming Paradigms

    Publications:

    Conferences:

  • Formal Verification of Pipelined Processors with Precise Exceptions,
    K. Kalyanasundaram and R. K. Shyamasundar, In ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), San Diego, May 2004

    • Journals:

    Book Chapters:

  • Verification of Clock Synchornization in TTP,
    K. Kalyanasundaram and R. K. Shyamasundar, In Formal Models, Languages and Applications, World Scientific - Series in Machine Perception & Artificial Intelligence (ISBN 981-256-889-1), Vol. 66, 2006.

    Awards and Honors:

  • Motorola UPR Fellowship
  • Bose Ramgnosi Indo-Trento Partnership for Advanced Research (ITPAR) Fellowship

    Skills:

    Programming Skills: C, C++, OCaml, Verilog HDL
    Verification Tools: NuSMV, STeP, Esterel & Lustre, Cadence FormalCheck

    References:

    Available upon request

    Contact:

    K. Kalyanasundaram
    A-212, School of Technology and Computer Science (STCS)
    Tata Institute of Fundamental Research
    Dr Homi Bhabha Road, Navy Nagar, Colaba
    Mumbai 400 005
    India
    email: kalyan[AT]tifr[DOT]res[DOT]in

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