• My Die Area Estimation presentation slides based on the book "The Art of ANALOG LAYOUT" by Alan Hastings, Prentice Hall, Upper Saddle River, NJ, 2001

Introduction

The main problems of layout for analog/mixed signal ICs are device matching and unwanted parasitics reduction. Generally speak, the principle of mixed signal layout is noise (offset can treated as a sort of noise) reduction. Sometimes chip area may also be a concern. For matching, the techniques are common-centroid and interdigital, which can be used seperately or in combination, as well as dummy devices and device unitization. If there are no parasitics, then there is no noise coupling. The parasitics reduction techniques include, name a few but not the least, shield, guardring, long distance between noisy digital circuitry and the quiet analog one, etc.

Element Matching
The device mismatch is due to a number factors: local process variation, global lithographic variations, local lithographic variations and process gradients. These factors affect all devices: transistors, resistor, capacitors, and therefore similliar techniques can be used to match all elements.

Local process variations
All process parameters display

Global process varions
 

Process gradients

Basic Layout Concepts

• Stick Diagram
• Multi-finger Transistor.
• Power Sharing, Source-drain Sharing

Rules of Thumb from "IC Layout Basics, A Practical Guide".

• There is no such thing as too many tie-downs
• Whereever there is any space in an N-well, put a well tie. Wherever there is any space in the substrate, put in a substrate tie.
• Place your well ties and substrate contacts before you do any wiring.

More about substrate and well tie from "Principle of CMOS VLSI Design",by N.H.E Weste and K. Eshraghian

• Every well must have a substrate contact of the approciate type.
• Every substrate contact should be connected to metal directly to a supply pad (i.e., no diffusion or polysilicon underpassed in the supply rails).
• Place substrate as close as possible to to the source connection of transistors connected to supply rails. A very conservative rule would place one substrate connect for every supply (Vss and VDD) connection.
• Otherwise a less conservative rule is place a substrate contact for every 5-10 transistors or 25-100um.
• Lay out n- and p-transistors with packing of n-device toward VSS and packing of p-device toward VDD. Avoid "convoluted" structures that interwine n- and p-devices in checkboard styles.

Aetenna Effect notes

When RIE (reactive ion etching) is used to etch poly and metal1, charges builds on the unetched poly and metal1. This charge build-up can damage the transistor gate. Design rule usually define the maximum value of sigle gate structure. "Splitting large poly areas into smaller poly areas protects the poly during the poly etch." Charge build-up on metal1 could damage the gate too. "Gate tie-downs (NAC, Net Area Check) protect poly during metal one etch." (IC Layout Basics, A Practical Guide).

Diva Physical Verification notes

The most important concepts, I think, are layer processing and device recognition. There are three groups of layers:

• Original graphics layers
• Drived layers
• Connected layers (layers processed with the geomConnect command)

Physical verification steps:

1. Layer processign
2. DRC
3. Device recognition (Parameter and parasitics extraction)
4. LVS

1. DRC Rule File
2. Extraction Rule File
3. LVS Rule File

FAQs and advanced topics

1. How to implement density check using Diva?

1. Dan Clein, Gregg Shimokura, "CMOS IC Layout, Concepts, Methodologies, and Tools", Newnes, Boston, 2000, ISBN: 0-7506-7194-7
2. Christopher Saint, Judy Saint, "IC Layout Basics, A Practical Guide", McGraew- Hill, New York, 2002, ISBN: 0-07-138625-4
3. Christopher Saint, Judy Saint, "IC mask design : essential layout techniques ", McGraew-Hill, New York, 2002, ISBN: 0-07-138996-2
4. R.S. Soin, F. Malberti, and J. Franca, "Analog-Digital ASICs, Circuit techniques, design tools and applications", Peter Peregrinus, England, 1991
5. Mohammed Ismail, Terri Fiez, "Analog VLSI, Signal and Information Processing", McGraw-Hill, New York, 1994,ISBN 0-07-032386-0, Chapter 16, "Analog and Mixed Analog-Digital Layout", by Umberto Gatti and Franco Maloberti
6. Roubik Gregorian, Garbor C. Temes, "Analog MOS Integrated Circuit for Signal Processing", John Wiley & Sons, New Yor, 1987, Chapter 7, section 5, (layout considerations in switched-capacitor circuits)
7. R.S. Soin, F. Malobeerti and J. Franca edited, "Analogue-Digital Asics: Circuit Techniques, Design Tools and Applications " IEE Publishing, 1991, Chapter 10, "Practical Aspects of Mixed Analogue and Digital Design, by Paul O'Leary.
8. J.E. Franca, Yannis Tsividis, edited, "Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing", Second Edition, Prentice Hall, 1994, Chapter 11 by Franco Maloberti, "Layout of Analog and Mixed Analog-Digital Circuits".
9. Alan Hastings, Roy Alan Hastings, "The Art of Analog Layout", Prentice Hall; 1st edition (December 15, 2000) ISBN: 0130870617. (Great book name but no so great book).
10. Cadence, "Diva^® Refererence", Nov. 2002
11. Cadence, "Cell Design Tutorial", Jan. 2001
12. Cadence, "Virtuoso^® Layout Editor Training Manual", Feb. 1999