TRUTH TABLES

And

TIMING DIAGRAMS

 

Putting a 1 or 0 at the input of a gate can be done by applying a voltage (1) or an earth or 0 volts (0).

A switch can change the voltage at the inputs. Sometimes a data stream or a series of pulses arrive at gate inputs.

We can simulate a data stream but using a waveform generator and an oscilloscope to “see” what the stream looks like.

 

Truth tables give us the gate rules. Timing diagrams can demonstrate these rules in picture form. Timing diagrams can be very useful when trying to describe circuits that have MEMORY like flip flops. Read the timing diagrams from left to right and imagine a stream of pulses being applied to the inputs. The pulse streams shown are stepping through the binary numbers.

 

The symbols shown below are called distinctive symbols. There are other logic symbols used that are rectangular in shape.

[ieeesym1.gif]

 

The outputs are written using digital language.  The truth tables and timing diagrams substitute the letter C as the output for simplicity.

 

Apart from the NOT gate there are 2 inputs so only 4(22) combinations. The easiest way to make sure that you write down all combinations is to count in binary 00,01,10 and 11. If there were 3 inputs then there would be 8(23) combinations, 000,001,010,011,100,101,110 and 111.

 

 

AB is 1 only when A and B are 1

 

A

B

C

0

0

0

0

1

0

1

0

0

1

1

1

 

and

 

 

 

 

End cycle

 

 

 

 

 

B    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

not AB is 0 only when A and B are 1

 

A

B

C

0

0

1

0

1

1

1

0

1

1

1

0

 

nand

 

 

 

 

End cycle

 

 

 

 

 

B    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A+B is 0 only when A and B are 0

 

A

B

C

0

0

0

0

1

1

1

0

1

1

1

1

 

or

 

 

 

 

End cycle

 

 

 

 

 

B    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

not A+B is 1 only when A and B are 0

 

A

B

C

0

0

1

0

1

0

1

0

0

1

1

0

 

nor

 

 

 

 

End cycle

 

 

 

 

 

B    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AÅ B is 1 only when A is different to B

 

A

B

C

0

0

0

0

1

1

1

0

1

1

1

0

 

xor

 

 

 

 

End cycle

 

 

 

 

 

B    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

not AÅ B is 1 only when A is the same as B

 

A

B

C

0

0

1

0

1

0

1

0

0

1

1

1

 

xnor

 

 

 

 

End cycle

 

 

 

 

 

B    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

not A is always the opposite to A

 

A

C

0

1

1

0

 

not

 

 

End cycle

 

 

 

 

 

 

 

A    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

    

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