Updated July 23, 2001
Copyright 2001Chandranath.M
These PERL scripts are helpfull for easy conversion which you may come across in Image Processing. Helpfull for UNIX users.
1.1 Decimal(ASCI) to Hexadecimal Conversion
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#!/usr/sys/bin/sun4/perl
# variables
while(<>){
foreach(@_){
if($place_1==15) {$place_1 = "F";}
if($place_0==15) {$place_0 = "F";}
print $place_1.$place_0." ";
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TheseVerilog Files are helpfull for Simulation Testbenches which you may come across in Image Processing.
2.1 Test bench for Video SYNC and Data genarator
| Will be uploaded soon |
2.2 Standared RGB Color Bar Genarator
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/*-------------------------------------------------------------/
FILENAME: rgb.v OBJECTIVE: To generate RGB standared Color Bar ppm file AUTHOR :Chandranath.M DATE: 11-07-2001 --------------------------------------------------------------*/ module t_rgb ; reg CLKI ;
reg [7:0] G, B, R ; integer i;
parameter XSIZE = 'd80;
initial
initial
for ( i=0; i #(PERIOD*BARWID)
R = 8'b1111_1111;G = 8'b1111_1111;B = 8'b0000_0000; // yellow
#(PERIOD*BARWID)
R = 8'b0000_0000;G = 8'b1111_1111;B = 8'b1111_1111; // cyan
#(PERIOD*BARWID)
R = 8'b0000_0000;G = 8'b1111_1111;B = 8'b0000_0000; // green
#(PERIOD*BARWID)
R = 8'b1111_1111;G = 8'b0000_0000;B = 8'b1111_1111; // magenta
#(PERIOD*BARWID)
R = 8'b1111_1111;G = 8'b0000_0000;B = 8'b0000_0000; // red
#(PERIOD*BARWID)
R = 8'b0000_0000;G = 8'b0000_0000;B = 8'b1111_1111; // blue
#(PERIOD*BARWID)
R = 8'b0000_0000;G = 8'b0000_0000;B = 8'b0000_0000; // front
porch
#(PERIOD*BARWID);
DENB=1'b0;
initial
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2.3 Standared YCbCr color bar Genarator
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/*-------------------------------------------------------------/
FILENAME: ycbcr.v OBJECTIVE: To generate RGB standared Color Bar ppm file AUTHOR :Chandranath.M DATE: 11-07-2001 --------------------------------------------------------------*/ module t_ycbcr ;
parameter XSIZE = 'd80;
initial
initial
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TheseVerilog Files are helpfull forConversion from one format to another format which you may come across in Image Processing.
3.1 Conversion from .PPM format to .DAT format
| Will be uploaded soon |
4. Click the link bellow to get Conversion(RGB<->YCbCr) programs
| conversion.zip |
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SHELL SCRIPTS set filec ################################################## #set prompt="chida@`hostname`>" source /usr/slti/sys/shell/Cshrc #set prompt = "$cwd:t %" ####### FOR GCC ################################## set path=($path /usr/local/bin) set path=($path /users/ravindra/editors/vim61_my/bin) set path=($path /home/matlab6p1/bin) ############ FOR CVS ############################# alias less "/users/chida/less/less-358/less $1" alias setlib "/users/chida/setlib" #setenv LSI_DESIGN_LIB "TSMC18"#"HD06M" ####### FOR PROMPT PATH DESCRIPTION ############## #set prompt = "`hostname`:`pwd`>" set prompt = "chida@`hostname`>:`pwd`>" ####### FOR PROMPT PATH DESCRIPTION ############## alias cd 'cd \!*;set prompt = "chida@`hostname`:`pwd`>"' cd ####### FOR SIGNALSCAN ############################# alias disp "setenv DISPLAY toki:0.0" alias ss "signalscan &" ###########VI editor################## setenv EXINIT "set nu" ####### GENERAL COMMANDS ############ GENERAL COMMANDS ############ GENERAL COMMANDS ##### #alias vi "vim $1" alias cls "clear" alias lt "ls -alFt |more" alias edit "/users/chida/nedit-5.5/nedit $1" alias l "ls -lt|more" alias prc "ps -ef|grep " alias rbk " \rm *.bck " alias rsig " rm *.dsn *.trn " alias rlog " rm *.log " alias veriq "veri_lic_check" alias lchk "license.check" alias dcq "syn_lic_check " alias ftp159 "ftp 10.31.32.51" alias tel159 "telnet 10.31.32.51" #alias verilog "/users/chida/verilog $1" alias windows "/usr/lib/ICAClient/wfcmgr &" alias xv "/users/chida/xv-3.10a/xv" alias dcr "dc_shell -f $1 >dcr.log &" alias ncsius "source /home/cadence/IUS5.3/cshrc.verilog" alias ncsldv "source /home/cadence/ldv5.1/cshrc.verilog" alias ncv "ncverilog +access+rwc $1 +licq+ " alias matlab "/home/matlab/bin/matlab &" ----------------------------------------------- SYNTHESIS SCRIPTS read -f verilog /projects/dsphw/lc749451/users/chand/zsubmod/FMCNTPGEN/FMCNTPGEN.v analyze -f verilog /projects/dsphw/lc749451/users/chand/zsubmod/FMCNTPGEN/FMCNTPGEN.v remove_license HDL-Compiler current_design FMCNTPGEN check_design uniquify link create_clock -period 20 -w {0 10} CLK set_clock_skew -uncertainty 0.25 CLK set_fix_hold CLK create_clock -period 20 -w {0 10} XTAL set_clock_skew -uncertainty 0.25 XTAL set_fix_hold XTAL set_max_transition 1.0 XRST set_max_fanout 1 XRST derive_clocks set_input_delay 1.0 all_inputs() -clock CLK set_output_delay 3 all_outputs() -clock CLK set_input_delay 1.0 all_inputs() -clock XTAL set_output_delay 3 all_outputs() -clock XTAL check_design if(dc_shell_status == 0) { exit } set_max_area 0 set_operating_conditions -min best_case -max worst_case set_operating_conditions slow compile ungroup -all -flatten set_wire_load_model -name tsmc13_wl10 target_library = {"slow.db"} link_library = {"slow.db"} set_max_transition 1.8 find(design,"*") create_clock -period 10 -w {0 5} CLK create_clock -period 24 -w {0 12} XTAL compile -incremental -map_effort high report -constraint -verbose -all_violators > FMCNTPGENviol.rep report -area > FMCNTPGENarea.rep report_reference > FMCNTPGENref.rep report_timing -nworst 10 > FMCNTPGENtime.rep report -cell > FMCNTPGENcell.rep get_license HDL-Compiler write -f verilog -o FMCNTPGEN.net exit HDL SCORE SIMULATIOn SCRIPT FILE ---------------------------------------------- /* call instrumentation code generation and setting script */ hdli ./script/hdli.cf /* change directory to output */ cd output /* call script for simulation with testbench-1 and tclconfigfile */ ../script/hdls.cf /* change directory to report */ cd ../report /* call script for code/fsm coverage report generation */ hdlr ../script/hdlr.cf ############################################################################## # File : hdli.cf # Purpose : This script generates instrumented code for RTL coverage analysis. ############################################################################## # set the design name as hdls set_design_name hdls # Compile the RTL compile /projects/dsphw/lc749451/kijutu/FMTCNV/FMCNTPGEN.v # Tool setting for details of each command refer manual set_toggle_scoring -off set_library_selection -off set_scoring_style -vector set_implicit_block_scoring -on * set_hit_count_limit 1 set_gates_enabled -off * set_coverable_operators -bitwise -xor -reduction -logical -relational -event set_coverable_statements -assign -control -procedural -module -initial set_default_case_scoring -on deselect_coverage -module -block -path -expr -nlevel -gate -variable * select_coverage -module -block -path -expr -nlevel -gate -variable * extract_fsm -auto select_fsm_coverage * set_simulation_coverage_control -off query -A > ./hdls_work/hdls.sif # generate instrumented codes (.vin) generate_instrumented_code hdls ############################################################################### #simulation ############################################################################### ncverilog -f ../list_sim \ /users/rahul/lib/xilinx_lib/glbl.v \ -v /users/rahul/lib/xilinx_lib/simprims.v \ -v /users/rahul/lib/xilinx_lib/unisims.v \ -v /projects/dsphw/lc749451/kijutu/QIMP/QIMPYUV2TO4.v \ -v /projects/dsphw/lc749451/kijutu/QIMP/QIMP.v \ ../hdls_work/hdls.vin \ +togl+logfile=vertoggle.log +togl+master=vertoggle.mst \ +loadpli1=/home/cadence/IUS5.3/tools.sun4v/ict/Solaris/pli/ncv1_21/hdlspli.so:hdlscore_bootstrap \ +togl+workdir=toggle_work +togl+limit=1 \ +ncsimexe+/home/cadence/IUS5.3/tools.sun4v/inca/bin/ncsim \ +access+rwc \ +ncelabexe+/home/cadence/IUS5.3/tools.sun4v/inca/bin/ncelab \ +hdls+config+../config/tclconfigfile_1 \ +licq ############################################################################# # File : tclconfigfile_1 # Purpose : tcl configuration file for simulation with 1st set of test vector ############################################################################ # load the design load_design ../hdls_work/hdls.dgn # load the coverage file load_coverage ../hdls_work/hdls.cov # Save the code coverage file save_coverage -code /projects/dsphw/lc749451/hdlscore/FMCNTPGEN/hdls_work/hdls.sim_1.cov # Save the fsm coverage file save_coverage -fsm /projects/dsphw/lc749451/hdlscore/FMCNTPGEN/hdls_work/hdls_1.fsm set_expr_eval_limit 0 ##################################################################### # File : hdlr.cf ##################################################################### # load the design (.dgn) load_design /projects/dsphw/lc749451/hdlscore/FMCNTPGEN/hdls_work/hdls.dgn # load the code coverage file (.cov) for simulation - 1 load_coverage /projects/dsphw/lc749451/hdlscore/FMCNTPGEN/hdls_work/hdls.sim_1.cov # load the code coverage file (.cov) for simulation - 2 # union union.cov set_legend -off # generate code coverage report in summary report_summary -instance -showzero -bpev *... > sum_coverage.rep # report_summary -module -bpev * > INPSEL_sum_coverage.rep # load the fsm coverage file (.fsm) for simulation - 1 load_coverage -fsm ../hdls_work/hdls_1.fsm # load the fsm coverage file (.fsm) for simulation - 2 #load_coverage -fsm ../hdls_work/hdls_2.fsm # generate fsm coverage report in summary report_summary -module -saq * > sum_fsm.rep # generate detail code coverage report cor uncovered logic report_detail -module -bpesaq * > sum_fsm_detail_cov.rep LEC DO FILE -------------------------------------------------------------------- set log file ./verplex_v.log -replace set system mode setup read library -Both -sensitive -Verilog \ /usr/sanyo/verilog/lib/tsmc018/stdcell/macrocell.v \ /usr/sanyo/verilog/lib/tsmc018/stdcell/iocell.v \ /usr/sanyo/verilog/lib/tsmc018/stdcell/iocell_analog.v \ set undefined cell black_box //set flatten model -latch_fold //add substitute model PH2PSD PH1P read design -Verilog -Golden -sensitive \ ./qskin_imp.v read design -Verilog -Revised -sensitive \ ./qskin_imp.net.v \ ./qskin_imp.wrap.v set system mode lec add compared points -all compare report modules -up -Both report black box -class Full -Both -Module report cut point -Both report design data -summary -nokey_point -Both report environment report floating signals -Undriven -Both -Full report instance constraints -Both report instance equivalences -Both report message -Design -Both -Nosummary report notranslate modules report pin constraints -module -Both report pin equivalences -module -Both report primary inputs -class Full -Both report primary outputs -class Full -Both report renaming rule -Full -Both report search path report tied signals -Net -class Full -Both report unmapped points -extra -unreachable -notmapped write hier dofile dofile.hier -Black_box -Exact_pin_match -NOConstraint -Threshold 50 -Rep exit -f |
| Will be uploaded soon |