 | Low Power Design -
Circuit and Transistor level
 | Issues of Power dissipation at Transistor
level. Novel Flip Flop design for high speed low power application.
Techniques like transistor scaling and usage of NMOS philosophy in
CMOS transistors for better performance. (See
publication 1 and 2 for details) |
|
| Design for Manufacturability -
Gate and Physical Level
| Possibility of a billion transistors on a
chip make the process of routing and placement increasingly
difficult. Also, since these issues come last in the design cycle,
they are very costly to fix. Hence for the modern VLSI system,
routability is not only a tight design constraint but also typically
very time consuming. I like to work on Gate level and Physical level
techniques like regularity extraction, signature based synthesis for
prediction of successful (or failing) layout at an earlier stage and
for optimizing the task of physical synthesis by incorporating the
information of regularity in it. |
|
| Image Compression -
Context driven compression and multiple scheme
:
| Data compression usually works by applying
transforms to images and removing redundant data. However if a
framework can define "redundant" for users, lossless (wrt
Information not Data) compression in that framework can achieve
10000X. Research is needed in this field to find out how we can
classify and partition redundancy in most of the applications. |
| What stops us to apply lossy highly
compressed transforms to some parts of the image and low compression
lossless transforms to other parts. How will be the framework as
described above help us in this regard. |
|
Publications -
| XXXX, IEEE Transactions on Circuits and Systems |
| XXXX, Proceedings of PATMOS 03 held at
Polytecno Di Torino, Torino, Italy. |
| "Novel Static Flip Flop Design by feedback
restructuring" , In correspondence |
|
