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Name : Prasad Vivek Chandrashekhar E-mail : [email protected] Cell no: 09860565445 Experience : Total about 4 years of experience in VLSI Design. Good Experience in VHDL and Verilog HDL coding. Good exposure to various EDA tools for design, synthesis and simulation. Expertise on Linux and knowledge in Perl. Projects (Reverse Chronological Order): #1. Gigabit Ethernet (onsite-offshore): Site : Network Programs (Noida) Team Size : 3 Engineers. Period : September 2005 - May-2006. Duration : 9 months Platform : Intel Pentium Operating System : Linux – RedHat 9.2 Design Tools : Specman Elite 5.0, Modelsim 6.1 Description: The operating speed is 10, 100 and 1000 Mbps. It has a OCP interface on the top side and GMII interface at the PHY side. It receives and transmits correctly formatted packets, supports frame bursts, frames with extension, magic packet, and jumbo packet. Responsibilities: Verification SRS, Feature Extraction and Test-Case List, GEMAC Receiver module and Checksum block Verification in Specman-‘e’. Developed Verification SRS at the client side Canon, Japan. #2. IEEE 1394 (Fire-Wire Link Layer Controller): Site : Silicon Interfaces Team Size : 1 Engineer. Period : May 2005 - September 2005. Duration : 3 months Platform : Intel Pentium Operating System : Linux – RedHat 7.2 Design Tools : Specman Elite 4.0, Modelsim 5.8b Description: It is a high-speed serial bus protocol. The Link Layer controller allows easy integration into an IO sub-system. It supports bus speed of 100, 200 and 400 Mbps. It has a 32-bit host layer interface and 8-bit physical layer interface. It has software adjustable FIFOs. It receives and transmits correctly formatted 1394 packets and generates and inspects the 32-bit Cyclic Redundancy Check. Responsibilities: Verification of 32-bit CRC module, FIFO using ‘e’ and Specman Elite. #3. UART (Universal Asynchronous Receiver Transmitter): Site : Silicon Interfaces Team size : 1 Engineer. Duration : 3 Months Period : May 2005 – September 2005. Platforms : Intel Workstation Operating Systems : Linux – RedHat 7.2 Design Tools : Specman Elite 4.0, Modelsim 5.8b Description: The SI40U550 IP core is a Universal Asynchronous Receiver Transmitter (UART) fully compatible with the defacto standard 16550 UART. The SI40U550 IP core performs serial to parallel conversions on data received from a peripheral device or modem & parallel-to-serial conversion on data received from the host. The host can read the UART status at any time. The SI40U550 IP core includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link. The core provides a full-featured transmitter-receiver pair, configurable by software for different speeds, character widths, parity etc. The receiver provides information status with several error indications. Responsibilities: Verification of transmitter modules using ‘e’ and Specman Elite 4.0. #4. PHY control Register: Site : Network Programs India. Team Size : 6 Engineer Period : September 2005 Duration : 3-days Platforms : Intel Pentium Operating Systems : Windows XP Design Tools : Xilinx 7.1i, Modelsim 6.1, Synplify 7.0 Description: GEMAC module is connected to the medium using PHY interface. For transmission PHY layer takes the frame from Tx module and gives it to PHY layer which performs the necessary encoding of the data received and puts this encoded data on the medium attached to it. While reception it will again decode any encoded data and give it to RX module. All this operations takes place in co-operation with PHY control register. Responsibilities: Design, coding and synthesis of PHY control register. #5. Hardware Implementation of Digital Neuron Chip for Handwritten Character Recognition: Site : A.I.C.T.E., New Delhi (Walchand College of Engineering). Team Size : 1 Engineer Period : October 2002 - May 2003 Duration : 8 months Platforms : Intel Pentium Operating Systems : Windows XP Design Tools : Xilinx 5.1i, Modelsim 5.6, Borland C Description: Implementation of Feed-Back Neural Network in an FPGA Device. Error Back-Propagation Algorithm of neural network was implemented in Xilinx FPGA XC2S100. The weights for the network were obtained using C-language and the same were used. Complete network was coded in VHDL and synthesized using Xilinx Synthesis Technology. Responsibilities: VHDL coding and implementation on Xilinx XC2S100 FPGA. #6. RISC Processor: Place : KBP College of Engineering, Satara. Team Size : 1 Engineer. Period : October 2001 - February 2002 Duration : 5 months Platforms : Intel Pentium Operating Systems : Windows 98 Design Tools : Xilinx 3.1i, Modelsim 5.5a Description: The modeling processor involves 8 instructions. Modules designed include concurrent structures, functional partitioning. This involved the modeling of Reduced Instruction Set Computer (RISC). Responsibilities: VHDL coding of complete RISC processor. #7. “Implementation of Digital Circuits using VLSI Technology”. Frequency Counter. Site : KBP College of Engineering, Satara. Team Size : 5 Engineers Period : August 2000 - April 2001 Duration : 9 months Platforms : Intel Pentium Operating Systems : Windows 98 Design Tools : Orcad, Xilinx 2.1i Description: Implemented a 3-digit frequency counter in Xilinx CPLD chip XC9572pc84 as a final year engineering project. The counter was very fast than any available frequency counter of same specification and was very portable. The project has received “First Prize” at an state-level project competition held in Ambajogai in March-2001. Responsibilities: VHDL, synthesis and simulation of frequency counter. Implemented on Xilinx XC9572 CPLD. Computer Skills: Computer System : Intel-based Pentium Operating System : Linux, Microsoft Windows NT / 2000, XP. Software Languages : Assembly Language, C, C++, VHDL, Verilog, Specman-e. Scripting Languages : Perl, Linux Bash Shell Script Design tool : Xilinx 6.1i, Modelsim 6.1, Leonardo Spectrum 2003, Quartus-II 5.0, Specman Elite 5.0. PERSONAL DETAILS: Name : Vivek Chandrashekhar Prasad Date of Birth : 03-12-1979 Marital Status : Single Nationality : Indian Religion & Caste : Hindu, Brahmin Permanent Address : Plot No. 16, Sai-Prasad Colony, Ambedere Road, Shahupuri, Satara-Pin: 415002 State: Maharashtra, India. Phone: +91-02162-250925 Languages Known : English, Hindi, and Marathi. Educational Qualification: B.E. Electronics from K.B.P College of Engineering, Satara. Percentage: 67.40%, Grade: Distinction. Prasad Vivek Chandrashekhar |