Sankaran Kartik Jayanarayanan
Email: [email protected]
11511 Metric Blvd. # 311, Austin, TX 78758.
Daytime Phone: (512) 471-8658, Home Phone: (512) 973-9534,
FAX (512) 471-5625
OBJECTIVE
Seeking a challenging position (or internship) in the R&D division
in the Semiconductor Industry.
PRESENT STATUS
Ph.D. student in Electrical Engineering (Solid-State Devices)
at the University of Texas at Austin.
TIME-LINE
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Aug. 1999 – Present : Research Assistant, Dept. of Elec. Eng., University
of Texas, Austin.
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Ph.D. Research topic: Analysis & study of vertical SiGe MOSFET’s. GPA:
4.0.
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June 2002 – Aug. 2002 : Summer Intern at MOTOROLA,
Austin, TX.
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Jan. 1998 – July 1999 : Process Control Engineer at ANALOG
DEVICES INC., Santa Clara, CA.
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Aug. 1995 – Nov. 1997 : M.S. in Elec. Eng., Auburn University, AL.
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MS. Thesis topic: Simulation and Measurement of SiGeC Heterostructure Devices.
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July 1991 – June 1995 : B.S. in Elec. Eng., Indian Institute of Technology
(IIT), Madras, India.
WORK EXPERIENCE, ANALOG DEVICES
INC. [Feb. 1998 – July
1999]
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Analysis of parametric electrical test data, providing regular feedback
to process engineers resulting in process improvement in Implant/Diffusion,
Poly/Oxide deposition, and masking issues.
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Learned the effects of various fabrication techniques on electrical test
parameters of a product and the relationship between parametric test data
and process flow.
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Worked closely with the Yield Enhancement group investigating the causes
of low yields of certain products and appropriately altered fabrication
processes to eliminate such problems.
INTERNSHIP EXPERIENCE, MOTOROLA
[June-Aug. 2002]
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Development of high-K gate dielectric materials such as Hf-oxide, Hf-silicates
and Hf-aluminates, working with the “MOSFET Materials Development &
Integration” (MMDI) group in Austin, TX.
LABORATORY EXPERIENCE
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Hands-on experience with UHVCVD, photolithography, oxidation, RIE.
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Electrical measurements using the KLA 3000 wafer prober coupled
with a Reedholm tester.
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Wafer probing and measurement using the HP 4155 Semiconductor Parameter
Analyzer.
COMPUTING AND SIMULATION SKILLS
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Languages: Fortran, Pascal, C.
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Tools: MEDICI, SUPREM, MAGIC, PSPICE, ATLAS.
PUBLICATIONS
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S. Jayanarayanan, F. Prins, X. Chen, S. Banerjee, "Enhanced
Mobility in 100 nm strained SiGe vertical PMOSFETs fabricated by UHVCVD,"
Materials Research Symposium, November 2001.
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X. Chen, K. Liu, Q.C. Ouyang, S.K. Jayanarayanan, S.K. Banerjee,
"Hole and Electron Mobility Enhancement in Strained SiGe Vertical MOSFETs,"
IEEE Trans. Electron Devices, Vol. 48, No.9, September 2001.
AWARDS/HONORS
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Ranked 28 out of 100,000 candidates in the IIT entrance exam, 1991.
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Ranked in the top 25 among 25,000 candidates in the Physics Talent Test
conducted by the Association of Physics Teachers of India.
REFERENCES available upon request.