Sankaran Kartik Jayanarayanan
Email: kartik@ece.utexas.edu
11511 Metric Blvd., Apt. 311, Austin, TX 78758.
Daytime Phone: (512)471-8658 
Home Phone: (512)973-9534
FAX: (512)471-5625

OBJECTIVE
 Seeking a challenging position in the Semiconductor
 Industry.

EDUCATION
* Ph.D., Electrical Engineering (Semiconductor
  Devices), University of Texas at Austin. GPA: 4.0.
  Thesis title: Analysis and study of SiGe vertical
  MOSFETs. Expected Graduation Date: December 2003. 
* M.S., Electrical Engineering, Auburn University,
  AL, December 1997. Thesis title: Simulation &
  Measurement of SiGeC Heterostructure Devices. 
* B.Tech. in Electronics and Communication
  Engineering, Indian Institute of Technology (IIT)
  Madras, June 1995.

WORK EXPERIENCE, ANALOG DEVICES INC. 
[Feb. 1998 - July 1999]
* Analysis of parametric electrical test data 
  using the KLA 3000 wafer tester, providing regular
  feedback to process engineers resulting in 
  process improvement in Implant/Diffusion, 
  Poly/Oxide deposition, and masking issues. 
  Learned the effects of various fabrication 
  techniques on the electrical test parameters of a
  product and the relationship between parametric 
  test data and the process flow. Used Statistical
  Process Control (SPC) and control charts in 
  data analysis. 
* Worked closely with the Yield Enhancement group in 
  investigating the causes of low yields of certain 
  products and appropriately altered the fabrication
  processes to eliminate such problems in the future.

INTERNSHIP EXPERIENCE, MOTOROLA 
[June - Aug. 2002]
* Development of high-K gate dielectric materials 
  such as Hf-oxide, Hf-silicates and Hf-aluminates,
  working with the "MOSFET Materials Development &
  Integration" (MMDI) group in Austin, TX. 

LAB EXPERIENCE
* Hands-on experience in UHVCVD, photolithography, 
  XRD, AFM, oxidation, RIE.
* Metrology Tools such as Ellipsometer, Nanospec, 
  Profilometer.
* Electrical Measurement and Characterization using 
  the HP 4155 Semiconductor Parameter Analyzer. 
* Electrical Testing using the KLA 3000 wafer 
  prober and Reedholm tester. 

COMPUTING AND SIMULATION SKILLS
* Languages: Fortran, Pascal, C. 
* Tools: MEDICI, SUPREM, MAGIC, PSPICE, ATLAS. 

PUBLICATIONS
* "Hole and Electron Mobility Enhancement in Strained 
  SiGe Vertical MOSFETs," IEEE Trans. Electron 
  Devices, Vol. 48, No.9, September 2001.
* "An Asymmetric Si/SiGe channel vertical p-type 
  metal-oxide-semiconductor field-effect transistor,"
  Solid-State Electronics, 45, pp. 281-285, 2001. 
* "Enhanced Mobility in 100 nm strained SiGe vertical 
  PMOSFETs fabricated by UHVCVD," Materials Research
  Society Symposium, Proc. Vol. 686, 2002.  

AWARDS/HONORS
* Ranked 28 out of 100,000 candidates in the IIT 
  entrance exam, 1991.
* Ranked in the top 25 among 25,000 candidates in the 
  Physics Talent Test conducted by the Association of 
  Physics Teachers of India.

REFERENCES  available upon request.