CURRICULUM VITAE

Sitikant Sahu

Permanent Address Plot no –245, Pal Heights Mayfair Road, Jayadev Vihar, Bhubaneswar-751013

Personal Details

   Telephone                      : (91)-(674)-2361361
   Email                           : [email protected].
   Language proficiency     : English, Hindi, and Oriya

Passport No : A-9819847 (Valid up to 26-7-2011)

Career Profile (B-Tech 1999-2003, Dept of Computer Science and Engineering, Indian Institute of Technology, Kharagpur.)

Educational Background

SLNO

DEGREE

BOARD

PERCENTAGE

MATRICULATION

ICSE

89.5

INTERMEDIATE

CHSE -ORISSA

80.5

B.Tech (Comp. Sc.)

IIT KHARAGPUR

(7.66/10)

Software Skills

Languages: C, Java, QBASIC, Unix Shell Programming, Microprocessor Programming for 8085 processor, Verilog HDL, SQL.

OS Familiarity: Linux, UNIX, Windows 98, 2000, professional and XP

Other Familiar tools: MATLAB, PSPICE, YACC, LEX, Rational Suite

Special Courses Taken (As Elective)

Advanced Graph Theory, Embedded Systems, Artificial Intelligence, Real Time systems, Network and Distributed File system and Machine Learning.

Projects Undertaken

1. Channel allotment in Mobile Network Communication System

(Summer 2001)

O/S: Linux

Language: C

Description:

Proposed an efficient algorithm with simulation for channel allotment in a mobile network system. The algorithm is supported with mathematical calculations and derivations.

2. Porting Kilo Virtual Machine for micro ITRON as OS (summer 2002 as a part of my industrial training).

Software: GNU Cross Compiler for SANYO hyperr Processor, Debugger for embedding the program into the microprocessor.

Hardware: SANYO Hyperr RISC Processor

O/S: Micro ITRON, Windows Professional for Serial Port Communication.

Language: C and assembly level for SANYO Hyperr RISC processor.

Description: Modeled KVM (Kilo Virtual Machine, an embedded version of Java Virtual Machine) in C language to make it compatible to micro ITRON Operating System on SANYO hyperr RISC Processor.

3. Design and implementation of ASIC (Application Specific Integrated Circuit) for encryption and Cryptanalysis (August 2002-April 2003).

(i) Cryptanalysis of Rijndael:

This part of the project involved study of different methods of cryptanalysis of Rijndael encryption algorithm (AES). A new method of cryptanalysis using intelligent database was used in making clusters. In this pattern of different cipher-plain text pair was analyzed and clusters were of keys were grouped different pattern. This cryptanalytic method is supposed to be independent from the number rounds of encryption done in the encrypting algorithm. Unfortunately, the memory space exploded. So, research is still going on controlling the memory space.

(ii) Key Agreement Protocol

In this a new key agreement protocol was proposed. This method is used for agreement of private keys without being hacked in the channel. The protocol used the concept of Cellular Automata. Several cryptanalysis tests were done to verify the security of the algorithm. It was found the algorithm was free from linear and differential cryptanalysis along with other standard cryptanalysis algorithm.

Projects as part of courses

· Implementation of Distributed File System at user level using socket system calls. In this project we implemented a cache server. It solved the cache inconsistency problem. It controlled the read-write hazards. (As part of course on Network and Distributed Systems)

· Implementation of a machine learning tool, which could perform different types of clustering algorithms, to classify different datasets. The clustering algorithms that were implemented are K-means, HAC and Buck-shot algorithm. (As a part of course, Machine Learning).

· Designed a chip for generation of Random Numbers using Cellular Automata. (As a part of System Design Lab).

· Designed a Simple Operating System (UNIX--) with support for multiple thread scheduling. The kernel had support features of complete semaphore library for interprocess communication, shared memory and event handler. Coding was done in C and assembly. (As part of course on Design of Operating Systems)

· Developed an Assembler, and a Linker for the Pentium processor in C language (as part of course on System Programming)

· Designed a 4-bit computer CPU with instruction set, a subset of 8085 processor. The processor could perform arithmetic and logic operations.(as a part of Hardware Design Lab).

· Designed a hardware circuit for Serial Communication using 8255 as interface and 8051 as micro controller. The communication is set between two equivalent hardware set, one transmitting characters and other receiving the characters and displaying using 7 segment Display.(as a part of Microprocessor Lab)

· Designed and analyzed various modulation schemes for analog and digital data communications. (As part of our communication lab).

· Designed a front-end compiler for a subset of C language. It involved design of Lexical Analyzer using LEX tools and then parser and semantic analysis using YACC tools. It takes a C program and coverts into 3-address code. (As a part of our compiler lab)

· Designed an interpreter for a subset of C in C using trees as data structures. It finds the first error, if no error is found, it executes the program. (As a part of our Programming and data structure lab)

· Designed basic electronic Circuits like amplifier, filters, registers, TTL gates, triggers, counters, etc. (as a part of linear electronics and digital electronics lab).

· Designed Automation Software for Library and Supermarket using JAVA with proper graphical user interface. It included writing of software requirement specifications (SRS) and making of UML diagram (class diagram, sequence diagram and collaboration diagram) using Rational Suite.

Academic Achievements

Secured All India Rank 269 (out of 125,000 approx.) in IIT Entrance Examination, Examination and 89th Rank in Orissa Engineering Examination and selected for B-Stat for ISI Kolkata.
Selected among top 200 in Physics Olympiad (IAPT) in year 1998.