General Details Name Pentium 4 (Mid Range) Pentium Xeon (High End) Codename A80528, Willamette (0.18 µm) Foster (0.18 µm Xeon) A80532, Northwood (0.13 µm) Family/Generation 80786, 7th Generation, MMX, SSE, SSE2 Vendor Intel Manufacturer Intel First Introduction Feb 20, 2000 (1.5 GHz demo @ IDF, 0.18 µm) Nov 20, 2000 (1.4 and 1.5 GHz PGA423) Jan 3, 2001 (1.3 GHz PGA423) Apr 23, 2001 (1.7 GHz PGA423) May 21, 2001 (1.4, 1.5, and 1.7 GHz PGA603) Jul 2, 2001 (1.6 and 1.8 GHz PGA423) Aug 13, 2001 (2.0 GHz demo @ Siggraph, 0.18 µm) Aug 27, 2001 (1.9 and 2.0 GHz PGA423 and µPGA478) Aug 28, 2001 (3.5 GHz demo @ IDF, 0.13 µm, super-cooled) Sep 25, 2001 (2.0 GHz PGA603) Physical Details Package Type 423 Pin PGA 478 Pin µPGA 603 Pin PGA Package Size 5.34 cm x 5.34 cm (PGA423) 3.50 cm x 3.50 cm (µPGA478) 5.34 cm x 5.34 cm (PGA603) Socket or Slot PGA423 µPGA478 PGA603 Transistors 42,000,000 (includes 12 K µOP TC + 8 KB L1d + 256 KB L2 Cache) Process Technology 6M, 0.18 µm, CMOS Die Size 217 mm² (0.18 µm) Electrical Details Split Voltage No (automatically determined via VID Pins) Core Voltage 1.75 V 1.70 V L2 Voltage same as Core Voltage I/O Voltage same as Core Voltage 3.3 V for SMBus (Xeon) Typical Power 48.9 W (1.3 GHz 0.18 µm PGA423 @ 1.70 V) 51.8 W (1.4 GHz 0.18 µm PGA423 @ 1.70 V) 54.7 W (1.5 GHz 0.18 µm PGA423 @ 1.70 V) 51.6 W (1.3 GHz 0.18 µm PGA423 @ 1.75 V) 54.7 W (1.4 GHz 0.18 µm PGA423 @ 1.75 V) 57.8 W (1.5 GHz 0.18 µm PGA423 @ 1.75 V) 61.0 W (1.6 GHz 0.18 µm PGA423 @ 1.75 V) 64.0 W (1.7 GHz 0.18 µm PGA423 @ 1.75 V) 66.7 W (1.8 GHz 0.18 µm PGA423 @ 1.75 V) 69.2 W (1.9 GHz 0.18 µm PGA423 @ 1.75 V) 71.8 W (2.0 GHz 0.18 µm PGA423 @ 1.75 V) 57.9 W (1.5 GHz 0.18 µm µPGA478 @ 1.75 V) 60.8 W (1.6 GHz 0.18 µm µPGA478 @ 1.75 V) 63.5 W (1.7 GHz 0.18 µm µPGA478 @ 1.75 V) 66.1 W (1.8 GHz 0.18 µm µPGA478 @ 1.75 V) 72.8 W (1.9 GHz 0.18 µm µPGA478 @ 1.75 V) 75.3 W (2.0 GHz 0.18 µm µPGA478 @ 1.75 V) 56.0 W (1.4 GHz 0.18 µm PGA603 @ 1.70 V) 59.2 W (1.5 GHz 0.18 µm PGA603 @ 1.70 V) 65.8 W (1.7 GHz 0.18 µm PGA603 @ 1.70 V) 77.5 W (2.0 GHz 0.18 µm PGA603 @ 1.70 V) Maximum Power 66.68 W (1.3 GHz 0.18 µm PGA423 @ 1.70 V) 71.05 W (1.4 GHz 0.18 µm PGA423 @ 1.70 V) 75.25 W (1.5 GHz 0.18 µm PGA423 @ 1.70 V) 69.65 W (1.3 GHz 0.18 µm PGA423 @ 1.75 V) 73.85 W (1.4 GHz 0.18 µm PGA423 @ 1.75 V) 78.75 W (1.5 GHz 0.18 µm PGA423 @ 1.75 V) 83.48 W (1.6 GHz 0.18 µm PGA423 @ 1.75 V) 87.85 W (1.7 GHz 0.18 µm PGA423 @ 1.75 V) 88.55 W (1.8 GHz 0.18 µm PGA423 @ 1.75 V) 92.23 W (1.9 GHz 0.18 µm PGA423 @ 1.75 V) 96.25 W (2.0 GHz 0.18 µm PGA423 @ 1.75 V) 76.13 W (1.5 GHz 0.18 µm µPGA478 @ 1.75 V) 80.33 W (1.6 GHz 0.18 µm µPGA478 @ 1.75 V) 84.18 W (1.7 GHz 0.18 µm µPGA478 @ 1.75 V) 88.20 W (1.8 GHz 0.18 µm µPGA478 @ 1.75 V) 96.60 W (1.9 GHz 0.18 µm µPGA478 @ 1.75 V) 100.45 W (2.0 GHz 0.18 µm µPGA478 @ 1.75 V) 70.89 W (1.4 GHz 0.18 µm PGA603 @ 1.70 V) 75.14 W (1.5 GHz 0.18 µm PGA603 @ 1.70 V) 83.98 W (1.7 GHz 0.18 µm PGA603 @ 1.70 V) 97.24 W (2.0 GHz 0.18 µm PGA603 @ 1.70 V) Cooling Required Clock Frequencies CPU Core Speed 1.3...2.0 GHz (PGA423) 1.5...2.0 GHz (µPGA478) 1.4, 1.5, 1.7, and 2.0 GHz (PGA603) L1 Cache Speed 1.0x Core Speed L2 Cache Speed 1.0x Core Speed External Bus Speed 100 MHz Quad-Pumped AGTL+ with VTT = VCC Core/Bus Ratio 13.0x, 14.0x, ..., 20.0x Miscellaneous usual Motherboard Single Processor PGA423 Single Processor µPGA478 Single or Dual Processor PGA603 usual Chipset Intel 82850 or 82860 (Direct RDRAM) Intel 82845 (SDR SDRAM)     Processor Core Generic Details RISC, Out-of-order and Speculative Execution Specific Details up to 126 µOPs In-flight up to 48 Loads In-flight up to 24 Stores In-Flight Registers 32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE and SSE2 128 Entry Integer Register File ??? Entry FP Register File Pipeline Depth 20 Stages (excludes ??? Decode Stages before Trace Cache) Instruction Decode 1x IA-32/Cycle Instruction Dispatch 6x µOPs/Cycle 3x µOPs/Cycle Limit imposed by Trace Cache Execution Units Port 0: Double-pumped ALU, FP Move/Store/FXCH Port 1: Double-pumped ALU, Slow ALU, FP Execute Port 2: Load Port 3: Store Execution Speed up to 6 µOPs/Cycle Instruction Retirement 3x µOPs/Cycle Processor Buses Address Bus Width 36 Bit Data Bus Width 64 Bit Physical Memory 2^36 Bit = 64 GB Virtual Memory (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) Multithreading SMT, using Hyper-Threading Technology Multiprocessing SMP, using integrated local xAPICs Power Management HLT, STPCLK, SMI/SMM, Sleep, Deep Sleep Automatic Clock Throttling prevents Overheating Processor Caches Level 0 N/A Level 1 Code 12 K µOP Trace Cache, 8-Way, 6 µOPs/Line, microcode is inserted both into and after TC, the built traces span accross taken branches, SMC on 4 KB granularity flushes the entire TC Data 8 KB, 4-Way, 64 Byte/Line, MESI, 1 Line/Sector, Write-Through, Pseudo-LRU, Non-blocking (up to 4 Load Misses), Dual-ported (1 Load and 1 Store), 2/6 Cycle Latency (Integer/FP), 16 Byte Path to FP Unit for Loads Level 2 Unified 256 KB, 8-Way, 64 Byte/Line, MESI, 2 Lines/Sector, Exclusive, Pseudo-LRU, Non-blocking, 64 GB cacheable, 7/7 Cycle Latency (Integer/FP), 256 Bit Bus, Data on every Cycle Processor Buffers Fill Buffer 4x 64 Byte WC Buffer 6x 64 Byte Code Prefetch 64 Byte, filled 32 Byte at a Time Data Prefetch up to 256 Bytes ahead, fills the L2 Cache but not the L1 Data Cache, 1 Stream per 4 KB Page (Load or Store), up to 8 Streams at a Time, never crosses 4 KB Page Boundary unless there are Demand Loads Branch Prediction Static Yes Dynamic 4,096 Entries, ???-Way, providing 16x 4-State Pattern Recognition SW Hints on Conditional Branches: Taken, Not Taken RSB 16 Entries TLB Code 64 Entries, Full, ??? Data 64 Entries, Full, ??? Instruction Set Regular IA-32 Floating Point Integrated Multi Media MMX, SSE, SSE2 Processor Modes Real, Protected, Virtual, Paging, SMM, Probe Mode