Problem statement: understanding registers ...variables from the context programming interfaces.
 
Opportunity a):  Innovative non updatable ...registers ...registers that hold the timestamp
              ...or other ....system hardware populated values ...i.e. non-updatable registers
              by a programmer   or dynamic system-constants ...referencable in code
              i.e. addressable as pointer to a dynamic[-system-]constant or a 
              reference to a dynamic[-system-]constant.

              Example usages: as published on this uri or url

                        opportunity_innovative_MP_modified_to_vary_clock_speed_cycle.txt,
                        opportunityi_innovative_time_stamp_CMOS_clocks.txt,
                        in the document below 797)
                        
                        ....quite a few ...information that is usually accessed using the
                             /proc filesystem ...

                        ....for realtime and embedded sytems variable like cpu temperatures,
                               etc.

Opportunity b): understand kernel architechtures ...and types of kernel threads

                further to as published in  opportunity_innovative_MP_modified_to_vary_clock_speed_cycle.txt,
                                            opportunity_innovative_time_stamp_CMOS_clocks.txt,
                                            as articulated in project.pdf para 757) [...197) ,249) 684) , 791)]

 
                in a Multi-processor environments ...innovative platform architecture

                ...allocate few processors to non-pre-emptive threads
                   allocate few processors to pre-emptive threads 
 
                   applying use-case modelling to 

                       a)arrive at weighted kernel thread and process priority table
                              ....unix standard round-robin-schedulers ,
                                   thread priorites and process (waits ...kind of nice, umask) in queue

                   
                       b)a master processor ...addressing the issues of thread priorities 
                         ...thread syncronization (ideally not required as in SMP)

                       c)a kernel module or kernel thread context or as part of the standard process-architechture
                          to address benchmarking of metrics ...to precision in the context
                          of MP and SMP ...

                       d)In the non-symmetric processing environment where each processor is processing seperate
                         process in context ....a seperate memory bank[s] to the processor [...also independent
                         or seperate swap or virtual-memory ...say as kind  a platter on a hard-disk ...or given
                         the custom built architecture ...a embedded platter or page-swapping ...given the context
                         sufficient memory is available]

                       e)A shared memory-bank for sharing data-structures ...say process priority table etc...
                         ....also deriving from stadarding locking kind scenarios (kind of flag) ....for maintaining
                         such a shared data structures ....also one may refer to what is termed as quorrum usually
                         implemented in what is termed as cluster computing

                       f) understanding the way the 'jobs' function .... understand how the 'trap' function
                          ....use 'trap' ...to shift focus required ...to a particular process ....when writing
                          a shell to such Multi-processor based architecture

                          ....also refer to 'opportunity_interface_shell_unix_perl.txt'


Opportunity c) : A innovative kernel architecture ...and a multi processor architecture

                 to leverage ....process level threads ....usually the requirement being
                 a mutex ....ability to have threads executed parallely.


Further to the specifications as published in the documents on this uri or url 

"opportunity_innovative_MP_modified_to_vary_clock_speed_cycle.txt",
"opportunity_innovative_time_stamp_CMOS_clocks.txt",
"opportunity_perils_date_timetamp_management.txt"

when designing  computing environments with multi-processor environments (assymmetric or asychronous processors) 

...the design of the Bus architecuture  can be borrowed or derived from how a scsi bus works and devices on scsi bus negotiate
for data communications


Opportunity d) further to as envisaged in the above opportunities a,b,c ...deriving from concepts of grid computing or

               architechture currently being marketed by sun as sunfire servers , e10k or ibm (p-series n above)  partitioning 


               derive a innovative architechture as envisaged in projects.pdf ...viz. much on the lines of thread-pools,
               ability to either predine at BIOS kind of a interface or a dynamical derivable algorithm ...ability to pre-allocate
               or dynamically allocate ...processor's from a thread-pool to a virtual-host viz. a partition or host based on the
               processing needs i.e. while storage/hard-disk ...certain resources that make-up a host remain the same ...ability
               to vary or allocate the processing power to a specific virtual host or partition based on the need or requests
               makes or offers a viable proposition.

                
               given the context how kernel module , time-slicing , a communication or protocol to exchange the metrics for allocation
               of processing power between the virtual-host's can be derived, also a exploitable standard/protocol in parallel computing,
             [ also check the scope or context of GAB used in veritas cluster or hacmp from IBM world computing for said ...exchange of 
               thread or priorities ...i.e. which virtual host gets ...how many processors ...allocated....

               for instance in a 3-tier architecture ...a query from database fetching the data ...a pre-processor on the server-side
               populating the templates with fetch data and returning to the client ...analyze ...understand the queing of the requests
               viz. requests comming from a web-cloud no of incomming-requests and no of outgoing-or-dispatched-or-served-requests]


Opportunity e) innovation in computing ...how a dice is modeled ...viz. input output avenues for a processor,
               ability handled multiple context's of execution ....understanding how thread's work ??

               read through the document projects.pdf(197), 203), 249),715),790),791), 848),878), 328) )

               understanding how the dc powered ...telephone ...exchange based systems are architected (circuitry)

               number of voltages required to implement various operations (bitwise operators) on the data.

               use-case-modeled product-design viz. the pcb circuitry on the mother-boards (multi processor environment's) i.e. BUS architecture
               that move's data from disk to RAM , RAM to processor[s] , RAM to output-destinations. In this to be noted number of instructions
               processed per nano-second ...i.e. 'n' bit computing(  the 'n' bit architecture of binary computing model translating or the 
               equivalent of a RAM architecture or model equivalent ...kind of the unix 'awk' splitting the chunk of data to be fetched by the
               processor from the RAM) ...doesn't mean unix-time-slicing ....multiple-processor's ...that can execute
               instructions from thread-pool[processes in waiting to be processed]...picked from a process-table ...based on process-priority.
 
               deriving from how parallel power-supply circuitry is implemented ....parallel series ...basic's of electricity , electrical circuitry
               ...locating a processor where a resistor is located ...and providing a independent or parallel output the processed data for
               synchronization to the disk (understanding the context of a process-its-memory-address-space, open-descriptor's ...what is
               analogous or synonmous at the kernel,OS-design) ...potentially a word of data that goes to the processor...just denote's execution
               context ...tagged to the data-to-be-processed, synchronized with the shared output-channel

               ....the hindrance or the limit factor of reading the data-seek's context from the disk ...i.e. bifurcate disk i/o ....ability 
               to circumvent the choking factor from disk I/O.

               reading through the document 'opportunity_dynamic_virtualization_storage_blueprint.txt'

               given the scope for parallel threads ...while the thread's implemented to date  have been virtual in context ,
               ...well ...ability to balance the parallel-processing among the thread's ....rather than just a processor that just has a
               higher processing power (context of design and implementation of Multiple-processor's in context) , including the scope
               and context of virtual-memory-caching(poplution of the disk data into active-bits ...RAM)

               read through the document ...'opportunity_innovative_MP_modified_to_vary_clock_speed_cycle.txt'


To be Rationalized: given the context of implementing MP based systems ...as envisaged above vis a vis.
                    the traditional unix timestamp(based on processor clock cycle) ....context of the counter int size.

                    with reference to most computing platforms in market ...which are mips based ...thus guaranteeing the
                    unique-ness of the timestamp when used or referenced in context of any process or thread ...used as 
                    a unique reference in the context of computing.

                    when implementing or using onboard BIOS based clock ....ability to implement a accessible dynamic-system-constant,
                    points to be addressed ability for multiple execution thread's in a truely parallel within a enclosure ...viz.  
                    the context of parallel thread ...ability to fabricate a pcb design  for the same, take into account in the computing
                    context the fact that timestamp alone doesn't count for a unique-ness(eg: usage in database for unique reference for
                    rows)

                    explore the viability 
                    --------------------
                    in the context of  parallel processing ...parallel thread's with multiple processors in a enclosure,
                    when fabricating the dice for processor's ...design or implement a thread or bus-architechture that ships or
                    transports ...timestamp in the dice [ as also where/if required  ...a bios-clock for each-processor context]
                    given the context ...pin-based on the lines of socket-70 ...that enable's reading extremely fast, much like
                    registers ...integral to a processor.


                    Given the context of kernel ...implementation of scheduler ...trigger ...precision.

 
                    Given the context of the threads usage in programming context viz. ability to logically break-down a task into
                    handlable chunk's of smaller-tasks, and their management ...viz.priority,synchronization,exchange of data ,
                    between threads ...scope ,limitations, potential of using true-ly parallel-processing using Multiple-processors.


                    one of the key design hurdles that need to be overcome while designing the MP architechture ...is the population
                    of active bits, location of the OS(bootable / onboard), given that a processor drive's the bit-flow i.e. consumption
                    of bits ....and movement of data from disk ....swap...virtualmemory/RAM , scope of resolving conflicts of simultaneous
                    acess to data on disk what is usually termed quorrum or claim on disk by a processor ...by rationing the access to
                    the disk where a conflict arises by using a stop-clock/high-speed-fluctuator in/alternating the circuit design.

                 

                                     
 
                  


Note: The above problem statement having been encountered in various scenarios
      and detailed in various 'Proof of concepts' as mentioned in 
      
       http://uk.geocities.com/ravivenkatus/projects.pdf
       http://ravishankarkv.tripod.com/projects.pdf
        ....apply appropriate
      'use-case' modeling, rationalize and arrive at a workable and feasible 
       solution both commercially and techinically viable.

       
      It is clearly being envisioned above that ...terms are as for profit
      basis and absorption of labor ...with work on site (labor being located
      at point of location of systems and devices being maintained) by any one 
      choosing to make or utilize the above opportunity further to as described
      in the document projects.pdf.



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