Layered Architecture Based Embedded System Software Development of Network Processor’s Feature Applications

Abstract
Embedded system software designers and developers are faced with an expanding array of challenges such as modeling heterogeneous concurrent application and capturing a correct programming model. Concept of software architecture is a cornerstone of modern software modeling thought. Software architecture has matured to encompass broad explorations of notations, tools and analysis techniques. Layered Software Architecture Approach (LSAA) is traditionally understood as the modular decomposition of the system in different layers (or levels).

Network processors are considered as the communication devices that have to operate on both heterogeneous hardware and software to meet the requirement of network environment. Combining the respective strengths of LSAA, Embedded System Software Development Life Cycle (ES-SDLC) and the features provided by Network Processors is the motivation behind our research effort. We demonstrate preliminary experiences implementing various Layer 2 and Layer 3 network features of Gigabit IP Router running on multiple Intel’s IXP1200 family Network Processors. Our Gigabit IP Router software architecture utilizing LSAA based ES-SDLC represents that proposed approach achieves flexible architecture compatible to highly re-configurable and reusable software.

Keywords - Architecture-based, embedded system software, Gigabit IP Router, layered, Network Processor.

An Abstract Layer Integration of Network Processor’s Feature Applications

Abstract
The embedded software development dedicated to Network Processor’s (NP’s) feature applications providing various internet services is expensive due to the unidentified integration constraints and unpredictable interactions. This high engineering risk and integration cost can be reduced significantly by introducing abstraction. In our research work, we propose an architectural abstraction to automate the integration process between control plane and data plane in layers. NP’s features are at certain level of abstraction in our Gigabit IP router software architecture. We demonstrate preliminary experiences designing various Layer 2 and Layer 3 data plane features running on multiple Intel® IXP12xx family NPs. Control plane functionalities reside within MPC8245 system processor. The software components are modeled utilizing Teja NP designer tool. We evaluate consistency of the architecture and reduced integration effort to illustrate the concept.

Dynamic Behavior of Microarchitecture Based Network Processor’s Data Plane Feature Components

Abstract. The rapid advancements of networking technology have boosted potential bandwidth introducing bottleneck at the crossing points where data traffic is intercepted or forwarded. Recently, there has been tremendous interest in speeding those nodes in terms of Network Processors (NPs) to handle data traffics. There is not a precise definition of NP or the functions it needs to perform due to which there is no performance data exist to aid in the decision of selecting processor architecture for next generation NP. This paper presents an approach that ensures consistent, reliable, and performance sensitive embedded software architecture framework combining the respective strengths of Micro-architecture (MA) based NP’s data plane features and widely used general purpose dynamic behavior modeling strategy. We demonstrate Gigabit IP Router (GIPR) distributed data plane components architecture designed using Teja NP design tool and developed utilizing Intel’s IXP1200 NP’s microcode instruction set (IS) justifying the theory behind proposed concept.

Reconfigurable Abstract Layer of Network Processor’s Feature Applications

Abstract
The architecture diversity and complexity of embedded system software dedicated to Network Processor’s (NP’s) feature applications motivate the need for introducing abstract layer reconfiguration of the underlying NP’s functionalities. Recently, the reconfiguration of embedded system software architecture at run-time has grown up considerably for the consistent and reliable evolutionary systems. Architectures must have the capabilities to react the dynamic and changing nature of the reconfigurable embedded systems dedicated to NPs. In this paper, we propose layered architecture based Gigabit IP Router application utilizing Intel® IXP1200 NP with dynamic reconfiguration capabilities. We demonstrate the execution model of reconfiguration manager between different network planes. The preliminary experiences illustrates that the goal of higher reconfigurability and lower development and maintenance costs are achieved with an example of Layer 3 forwarding component.

IMPLEMENTING DISTRIBUTED MPLS-DIFFSERV NETWORK PROCESSOR’S FEATURE

Abstract
Distribution of Network Processor’s (NP’s) feature applications increases the processing capabilities of internet traffic and available bandwidth. This paper represents MPLS-DiffServ feature of layered architecture based Gigabit IP Router (GIPR) embedded software distributed among multiple Intel’s IXP12xx family NPs. The DiffServ provides a scalable QoS architecture focuses to achieve QoS assurance and MPLS is widely utilized protocol for intra-domain routing offering flexibilities to enhance traffic engineering capabilities of next generation routers. We demonstrate the problems combining respective strengths of MPLS protocol and DiffServ and the effective resolution within GIPR software architecture framework.
Key Words - Layered Architecture, Differentiated Services (DiffServ), Gigabit IP Router (GIPR), Multi Protocol Label Switching (MPLS), Network Processor (NP), Quality of Service (QoS).