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     The most common and least expensive mechanism for error detection is the vertical redundancy check (VRC), often called a parity check. In this technique, a redundant bit, called a parity bit, is appended to every data unit so that the total number of 1s in the unit (including the parity bit) becomes even.

     Suppose we want to transmit the binary data unit 1100001 [ASCII a (97)]; see Figure 1.0. Adding together the number of 1s gives us 3, an odd number. Before transmitting, we pass the data unit through a parity generator. The parity generator counts the 1s and appends the parity bit (a 1 in this case) to the end. The total number of 1s is now four, an even number. The system now transmits the entire expanded unit across the network link. When it reaches its destination, the receiver puts all eight bits through an even-parity checking function. If the receiver sees 11100001, it counts four 1s, an even number, and the data unit passes. But what if the data unit has been damaged in transit? What if, instead of 11100001, the receiver sees 11100101? Then, when the parity checker counts the 1s, it gets 5, an odd number. The receiver knows that an error has been introduced into the data somewhere and therefore rejects the whole unit.

     In vertical redundancy check (VRC), a parity bit is added to every data unit so that the total number of 1s becomes even.

Figure 6 Even parity VRC concept

                

     Note that for the sake of simplicity, we are discussing here even-parity checking, where the number of 1s should be an even number. Some systems may use odd-parity checking, where the number of 1 s should be odd. The principal is the same; the calculation is different.

     The simplest error-detection scheme is to append a parity bit to the end of a block of data. A typical example is ASCII transmission, in which a parity bit is attached to each 7-bit ASCII character. The value of this bit is selected so that the character has an even number of 1s (even parity) or an odd number of 1s (odd parity). So, for example, if the transmitter is transmitting an ASCII G (1110001) and using odd parity, it will append a 1 and transmit 11100011. The receiver examines the received character and, if the total number of 1s is odd, assumes that no error has occurred. If one bit (or any odd number of bits) is erroneously inverted during transmission (for example, 11000011), then the receiver will detect an error. Note, however, that if two (or any even number) of bits are inverted due to error, an undetected error occurs. Typically, even parity is used for synchronous transmission and odd parity for asynchronous transmission.

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Performance

      VRC can detect all singer-bit errors. It can also detect burst errors as long as the total number of bits changed is odd (1, 3, 5, etc.). Let’s say we have an even-parity data unit where the total number of 1s, including the parity bit, is 6: 1000111011. If any three bits change value, the resulting parity will be odd and the error will be detected: 1111 111011:9, 011 0111011:7, 11 000 10  011:5-all odd. The VRC checker would return a result of 1 and the data unit would be rejected. The same holds true for any odd number of errors.

     Suppose, however, that two bits of the data unit are changed: 111 0111011:8, 11 000 11011:6, 10000 11010 :4. In each case the number of 1s in the data unit is still even. The VRC checker will add them and return tan even number although the data unit contains two errors. VRC cannot detect errors where the total number of bits changed is even. If any two bits change in transmission, the changes cancel each other and the data unit will pass a parity check even number of errors.

      VRC can detect all singer-bit errors. It can detect burst errors only if the total number of errors in each data unit is odd.