--8-bit ALU Model with carry lookahead
--Rachel Hadaway
--feb 28 2003
Library work;
use work.hadaway.all;
entity alu8b is
	port (A, B_IN : in bit_vector (7 downto 0);
		  ALU_CTRL: in bit_vector (2 downto 0);
		  Carry_out :out bit;
		 Zero, Overflow : out bit;
		  result2 : out bit_vector (7 downto 0)
		 );
	end entity alu8b;

architecture alu8b_arch of alu8b is
signal p_vec, g_vec, result: bit_vector (7 downto 0);
signal cin_2nd, g_duh, p_duh: bit;
signal c_2nd : bit_vector (4 downto 0);
signal g_2nd, p_2nd : bit_vector (3 downto 0);
signal c_vec : bit_vector (9 downto 0);
signal less_in, diffsig, zerosig : bit;

begin

	
 --for 2's complement, we invert and add 1.  if we need it to make a number negative
							-- here is the "add 1" since it always needs to go with invert.
	g_2nd(3 downto 2) <= "00";
	p_2nd(3 downto 2) <= "00";
	zerosig <= '0';
	alu0: alu1bcla port map(a(0), b_in(0), alu_ctrl(2), less_in, alu_ctrl(2), alu_ctrl(1 downto 0), result(0), p_vec(0), g_vec(0));
	alu1: alu1bcla port map(a(1), b_in(1), c_vec(1), zerosig, alu_ctrl(2), alu_ctrl(1 downto 0), result(1), p_vec(1), g_vec(1));
	alu2: alu1bcla port map(a(2), b_in(2), c_vec(2), zerosig, alu_ctrl(2), alu_ctrl(1 downto 0), result(2), p_vec(2), g_vec(2));
	alu3: alu1bcla port map(a(3), b_in(3), c_vec(3), zerosig, alu_ctrl(2), alu_ctrl(1 downto 0), result(3), p_vec(3), g_vec(3));
	cla1: cla4b port map(g_vec(3 downto 0), p_vec(3 downto 0), alu_ctrl(2), c_vec(4 downto 0), g_2nd(0), p_2nd(0));
	alu4: alu1bcla port map(a(4), b_in(4), c_vec(5), zerosig, alu_ctrl(2), alu_ctrl(1 downto 0), result(4), p_vec(4), g_vec(4));
	alu5: alu1bcla port map(a(5), b_in(5), c_vec(6), zerosig, alu_ctrl(2), alu_ctrl(1 downto 0), result(5), p_vec(5), g_vec(5));
	alu6: alu1bcla port map(a(6), b_in(6), c_vec(7), zerosig, alu_ctrl(2), alu_ctrl(1 downto 0), result(6), p_vec(6), g_vec(6));
	alu7: alu1bcla port map(a(7), b_in(7), c_vec(8), zerosig, alu_ctrl(2), alu_ctrl(1 downto 0), result(7), p_vec(7), g_vec(7));
	cla2: cla4b port map(g_vec(7 downto 4), p_vec(7 downto 4), c_2nd(1), c_vec(9 downto 5), g_2nd(1), p_2nd(1));
	cla3: cla4b port map(g_2nd(3 downto 0), p_2nd(3 downto 0), alu_ctrl(2), c_2nd(4 downto 0), g_duh, p_duh);
	carry_out <= c_vec(9);


diffsig <= a(7) xor (not b_in(7)) xor c_vec(8);

--test for overflow
overflow <= c_vec(9) XOR c_vec(8);

--test for less than
less_in <= diffsig xor (c_2nd(2) XOR c_vec(8));

result2 <= result;
--test for zero
zero <= (not result(0)) and (not result(1)) and (not result(2)) and (not result(3)) and (not result(4)) and (not result(5)) and (not result(6)) and (not result(7));


end architecture alu8b_arch;