--model of 1 bit ALU with lookahead carry
entity alu1bcla is
	port ( A, B_IN, CARRY_IN, LESS_IN, B_INVERT: in bit;
		  SEL : in bit_vector(1 downto 0);
		  RESULT, P_OUT, G_OUT : out bit);
end entity alu1bcla;

architecture alu1bcla_arch of alu1bcla is
signal B_MODIFIED : bit;
begin
	with B_INVERT select
		 B_MODIFIED <= B_IN when '0',
					   NOT B_IN when '1';
with sel select
		RESULT <= A AND B_MODIFIED when "00",
				  A OR  B_MODIFIED when "01",
				  (A XOR B_MODIFIED) XOR CARRY_IN when "10",
				  less_in when "11";			  
		
P_OUT <= A OR B_MODIFIED;	
G_OUT <=  A AND B_MODIFIED;		 

	
end architecture alu1bcla_arch;