SESSION PLAN
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Subject |
Year/ Sem |
Class |
Section |
Strength |
Load |
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|
L |
T |
P |
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Advanced
Computer Architecture |
4 / VII |
CSE |
|
|
3 |
3 |
- |
|
Sr.No. |
Topic |
Unit No. |
Ref. |
Date
Covered |
Assignment
Link |
Due Date |
Web link
for class notes |
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1 |
Introduction to Computer arch. and
m/c. some def. & terms |
1 |
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2 |
Interpretation & Micro prog., The instruction set |
1 |
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3 |
Basic data Types, Instructions |
1 |
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4 |
Addressing and memory, Virtual to
real mapping, Basic instruction timing |
1 |
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5 |
Time, area & Instn sets, Time, Pipelined Processors, optimum
pipelining |
2 |
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6 |
Cost area |
2 |
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7 |
Tech state of the art, economics
of a processor project |
2 |
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8 |
Instruction sets, processor
evaluation matrix |
2 |
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9 |
Cache Memory, basic notion, cache
organization |
3 |
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10 |
Adjusting data for cache orgn., write policies, Strategy for line replacement |
3 |
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11 |
Cache environment, other types of
cache, split I & D caches |
3 |
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12 |
Two level cache, write assembly
cache, cache ref for instructions |
3 |
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13 |
Tech dep.cache
considerations, virtual to real translation |
3 |
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14 |
Overlapping the T cycle in V-R Transllation. Design summary |
3 |
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15 |
Memory system design, physical memory,Processor memory interaction |
4 |
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16 |
Memory modeling using queuing
theory |
4 |
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17 |
Open closed and mixed queue models,
waiting time, performance & buffer size |
4 |
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18 |
Review
and selection of queueing models, processors with
cache. |
4 |
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19 |
Vector
Processors, Vector Memory |
5 |
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20 |
Multiple
Issue Machines |
5 |
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21 |
Comparing
vector and Multiple Issue processors. |
5 |
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22 |
Shared
Memory Multiprocessors, Basic issues |
5 |
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23 |
partitioning,
synchronization and coherency |
5 |
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24 |
Type
of shared Memory multiprocessors |
5 |
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25 |
Memory
Coherence in shared Memory Multiprocessors |
5 |
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