SESSION PLAN

 

Subject

Year/ Sem

Class

Section

Strength

Load

L

T

P

Advanced Computer Architecture

4 / VII

CSE

 

 

3

3

-

 

 

Sr.No.

Topic

Unit No.

Ref.

Date Covered

Assignment Link

Due Date

Web link for class notes

1

Introduction to Computer arch. and m/c. some def. & terms

1

 

 

 

 

 

2

Interpretation & Micro prog., The instruction set

1

 

 

 

 

 

3

Basic data Types, Instructions

1

 

 

 

 

 

4

Addressing and memory, Virtual to real mapping, Basic instruction timing

1

 

 

 

 

 

5

Time, area & Instn sets, Time, Pipelined Processors, optimum pipelining

2

 

 

 

 

 

6

Cost area

2

 

 

 

 

 

7

Tech state of the art, economics of a processor project

2

 

 

 

 

 

8

Instruction sets, processor evaluation matrix

2

 

 

 

 

 

9

Cache Memory, basic notion, cache organization

3

 

 

 

 

 

10

Adjusting data for cache orgn., write policies, Strategy for line replacement

3

 

 

 

 

 

11

Cache environment, other types of cache, split I & D caches

3

 

 

 

 

 

12

Two level cache, write assembly cache, cache ref for instructions

3

 

 

 

 

 

13

Tech dep.cache considerations, virtual to real translation

3

 

 

 

 

 

14

Overlapping the T cycle in V-R Transllation. Design summary

3

 

 

 

 

 

15

Memory system design, physical memory,Processor memory interaction

4

 

 

 

 

 

16

Memory modeling using queuing theory

4

 

 

 

 

 

17

Open closed and mixed queue models, waiting time, performance & buffer size

4

 

 

 

 

 

18

Review and selection of queueing models, processors with cache.

 

4

 

 

 

 

 

19

Vector Processors, Vector Memory

5

 

 

 

 

 

20

Multiple Issue Machines

5

 

 

 

 

 

21

Comparing vector and Multiple Issue processors.

 

5

 

 

 

 

 

22

Shared Memory Multiprocessors, Basic issues

5

 

 

 

 

 

23

partitioning, synchronization and coherency

5

 

 

 

 

 

24

Type of shared Memory multiprocessors

5

 

 

 

 

 

25

Memory Coherence in shared Memory Multiprocessors

5

 

 

 

 

 

 

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