I²C - Chapter 4

4.0) Extended addressing (10 bit address mode)

     Due to the increasing popularity of the I²C bus the address space is
     nearly exhausted.This starts posing problems for people currently in
     the phase of designing a new I²C compatible IC.
     Therefore the I²C standard has been adapted.

     A chip that conforms to the new standard receives 2 address bytes.
     The first consists of 5 * a ONE ,the 2MSB's of the address and the
     Read/Write bit. The second byte contains the LSB's of the address.

     -----------------------------------------------------------------
     !S! 1 1 1 1 1 A9 A8 R/W !WA! A7 A6 A5 A4 A3 A2 A1 A0 ! WA ! ......
     -----------------------------------------------------------------

     This scheme insures that the 0 bit addressing mode stays completely
     transparent for the other devices on the bus.
     Normally any new design should adept to this new addressing scheme.

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