The future of CMOS technology - References

by A. J. Maurijones

References

  1. Yuan Taur, Douglas A. Buchanan, Wei Chen, David J. Frank, Khalid E. Ismail, Shih-Hsien Lo, George A. Sai-Halasz, Raman G. Viswanathan, Hsing-Jen C. Wann, Shalom J. Wind, and Hon-Sum Wong, “CMOS Scaling into the Nanometer Regime,” Proc. IEEE 85, No. 4, 486­504 (1997). 
  2. Gordon E. Moore, “Cramming More Components onto Integrated Circuits,” Electron. 38, 114­117 (April 19, 1965). 
  3. Gordon E. Moore, “Progress in Digital Integrated Electronics,” Digest of the 1975 International Electron Devices Meeting, IEEE, New York, 1975, pp. 11­13. 
  4. H. C. Pfeiffer, R. S. Dhaliwal, S. D. Golladay, S. K. Doran, M. S. Gordon, T. R. Groves, R. A. Kendall, J. E. Lieberman, P. F. Petric, D. J. Pinckney, R. J. Quickle, C. F. Robinson, J. D. Rockrohr, J. J. Senesi, W. Stickel, E. V. Tressler, A. Tanimoto, T. Yamaguchi, K. Okamoto, K. Suzuki, T. Okino, S. Kawata, K. Morita, S. C. Suziki, H. Shimizu, S. Kojima, G. Varnell, W. T. Novak, D. P. Stumbo, and M. Sogard, “PREVAIL—A Next Generation Lithography,” J. Vac. Sci. Technol. B 17, 2840­2846 (November/December 1999). 
  5. Lloyd R. Harriott, “Scattering with Angular Limitation Projection Electron Beam Lithography for Suboptical Lithography,” J. Vac. Sci. Technol. B 15, No. 6, 2130­2135 (November/December 1997). 
  6. R. H. Dennard, F. H. Gaensslen, L. Kuhn, and H. N. Yu, “Design of Micron MOS Switching Devices,” presented at the IEEE International Electron Devices Meeting, December 6, 1972. 
  7. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions,” IEEE J. Solid-State Circuits SC-9, No. 5, 256­268 (1974). 
  8. J. H. Stathis and D. J. DiMaria, “Reliability Properties for Ultra-Thin Oxides at Low Voltage,” Proceedings of the 1998 International Electron Devices Meeting, IEEE, Piscataway, NJ, 1998, pp. 7.2.1­7.2.4. 
  9. J. D. Meindl, “Gigascale Integration: Is the Sky the Limit?” IEEE Circuits & Devices 12, 19 (November 1996). 
  10. Y. Taur, Y.-J. Mii, D. J. Frank, H. S. Wong, D. A. Buchanan, S. J. Wind, S. A. Rishton, G. A. Sai-Halasz, and E. J. Nowak, “CMOS Scaling into the 21st Century: 0.1 µm and Beyond,” IBM J. Res. Develop. 39, No. 1/2, 245­260 (1995). 
  11. T. N. Theis, “The Future of Interconnection Technology,” IBM J. Res. Develop. 44, No. 3, 379­390 (2000, this issue). 
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