Prince Sultan University

College for Women

 Department of Computer and Information Sciences

2nd Semester 2005 - 2006

 

 

COURSE OUTLINE

 

Course Code : CS151                                                           Pre-requisite : CS 101

Course Title    :Introduction to Digital Design                                                            
Name of Faculty: Sarab Al Muhaideb

Credit Hours    : 3                                                                   

 

 

I.     Course Description:  Digital design is concerned with the design of digital electronic circuits, which are employed in the design and construction of digital systems such as computers, data communication, digital recording, and many other applications. This course presents the basic tools for the design of digital circuits and provides the fundamental concepts used in the design of digital systems.

 

 

 

II.                  Course Objectives: 

 

Knowledge

-          Describe digital systems and digital computers and their components.

-          Learn different numbering and encoding systems, together with their operations.

-           

-          Understand the components of, Analyze, design and optimize Combinational Circuits.

-          Understand the components of, Analyze, design and optimize Sequential Circuits

 

 

Cognitive Skills

-           Use CAD tools to draw logic diagrams.

-          to enable the student to express real life problem in logic design terminology.

-           Utilize and modify fundamental combinational functions and their associated implementations.

 

Interpersonal Skills & Responsibility

 

 

Numerical & Communication Skills

 

 


 

 

III.    Course Content 

 

Topics

No. of Weeks

Contact Hours

1.      Digital Computers and Information

1.1.   Digital Computers
Information Representation
Computer Structure

1.2.   Number Systems
Binary Numbers
Octal and Hexadecimal Numbers
Number Ranges

1.3.   Arithmetic Operation
Conversion from Decimal to Other Bases

1.4.   Decimal Codes
BCD Addition
Parity Bit

1.5.   Gray Codes

1.6.   Alphanumeric Codes
ASCII Character Code

 

 

Week 1-2

 

 

8

2.      Combinational Logic Circuits

2.1.   Binary Logic and Gates
Binary Logic
Logic Gates

2.2.   Boolean Algebra
Basic Identities of Boolean Algebra
Algebraic Manipulations
Complement of a Function

2.3.   Standard Forms
Sum of Minterms
Product of Maxterms

2.4.   Two-Level Circuit Optimization
Cost Criteria
Two-Variable Map
Three-Variable Map
Four-Variable Map

2.5.   Map Manipulation
Essential Prime Implicants
Nonessential Prime Implicants
Product-of-Sum Optimization
Don’t Care Conditions

2.6.   Other Gate Types

2.7.   Exclusive –OR/ Exclusive-NOR Operator and Gates
Odd/Even Function

2.8.   High Impedance Outputs

 

Week 3-5

 

12

3.      Combinational Logic Design

3.1.   Design Concepts and Automation
Design Hierarchy
Top-Down Design
Computer Aided Design
Hardware Description Languages
Logic Synthesis

3.2.   The Design Space
Gate Properties
Levels of Integration
Circuit Technologies
Technology Parameters
Positive and Negative Logic
Design Trade-Offs

3.3.   Design Procedure

3.4.   Technology  Mapping
Cell Specifications
Libraries
Mapping Techniques

3.5.   Verification
Manual Logic Analysis
Simulation

 

Week 6-7

 

8

4.      Combinational Functions ad Circuits

4.1.   Combinational Circuits

4.2.   Rudimentary Logic Functions
Value-Fixing, Transformaing, and Inverting
Multiple-bit Functions
Enabling

4.3.   Decoding
Decoder Expansion
Decoder and Enabling Combinations

4.4.   Encoding
Priority Encoder
Encoder Expansion

4.5.   Selecting
Multiplexers
Multiplexer Expansion
Alternative Selection Implementations

4.6.   Combinational Function Implementation
Using Decoders
Using Multiplexers

 

 

Week 8

 

 

4

5.      Arithmetic Functions and Circuits

5.1.   Iterative Combinational Circuits

5.2.   Binary Adders
Half Adder
Full Adder
Binary Ripple Carry Adder

5.3.   Binary Subtraction
Complements
Subtraction with Complements

5.4.   Binary Adder-Subtractors
Signed Binary Numbers
Signed Binary Addition and Subtraction
Overflow

5.5.   Binary Multiplication

5.6.   Other Arithmetic Functions
Contraction
Incrementing
Decrementing
Multiplication by Constants
Zero-Fill and Extension

 

 

Week 9-10

 

 

8

6.      Sequential Circuits

6.1.   Sequential Circuit Definition

6.2.   Latches
SR and S’R’ Latches
D Latch

6.3.   Flip-Flops
Master-Slave Flip-Flops
Edge-Triggered Flip-Flop
Standard Graphics Symbols
Direct Inputs
Flip-Flop Timing

6.4.   Sequential Circuit Analysis
Input Equations
State Table
State
Diagram

6.5.   Sequential Circuit Design
Design Procedure
Finding State Diagrams and State Tables
State
Assignment
Designing with D Flip-Flops
Designing with Unused States
Verification

 

 

Week 11-12

 

 

8

7.      Review

Week 13

 

 

 

IV.    Course Components 

 

Component

Contact Hours

Lecture

35

Tutorial

13

Practical/Field

0

 

 

 

V.     Teaching Strategies (Indicate the teaching and student activities to be used to develop the kinds of learning involved in each learning domain).

               

              Domain

                   Strategy

Knowledge

Concept Presentation

Cognitive Skills

Hands-on demonstration of CAD tools,
Showing physical objects of models,

Model Simulation.

Interpersonal Skills & Responsibility

 

Numerical & Communication Skills

Manual Exercises

 

 


 

VI.    Course Requirements 

-          Two Major Exams and a Final Examination

-          Class participation in discussion  and writing (pop quizzes)

-          Quizzes

-          Weekly Assignments

 

VII.   Student Assessment

 

              A.   Assessment Task (Indicate the kind of assessment tasks to be used to measure student learning in each of the learning domain.  Example: quiz, oral examination,  group work, etc… ).

 

Domain

Assessment Task

Knowledge

Quizzes, Examinations, Assignments

Cognitive Skills

Quizzes, Examinations, Assignments

Interpersonal Skills & Responsibility

 

Numerical & Communication Skills

Quizzes, Examinations, Assignments

 

 

 

              B.  Schedule of Assessment 

 

 

Assessment

 

Assessment Task

 

Week Due

Proportion of Final Assessment

1

Quiz 1

Week 3

5%[*]

2

Quiz 2

Week 6

5%

3

Major Exam I

Week 8

20%

4

Quiz 3

Week 10

5%

5

Major Exam II

Week 12

20%

6

Weekly Assignments

Every Week from Week 2-12

15 %

7

Final Examination

End of Semester

35%

 


 

 

 

 

VIII.    Learning Resources

 

A.      References -

            
Textbook:

"Logic and Computer Design Fundamentals", Morris Mano and Charles Kime. 3rd Edition, Prentice Hall, 2004.


Recommended Reference:
"Digital Design" by M. Mano, Prentice Hall, 2001.
 

 

Course Home Page:

            Visit  http://www.geocities.com/pscw_cs151  to find course announcements, notes, important dates ,assignments, grades and more.


Companion Web Site:
http://www.prenhall.com/mano/

 
Computer Aided Design Tools:
Microsoft Visio®
Xilinix® Student Edition

Useful Sites:
www.radioshack.com

                www.jameco.com

            http://intel.com/

 

           

B.   Facilities Required -
        Electronic Lecture Class Room

 

 

 

 

 

 



[*] Lowest quiz is dropped from total

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