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                               The 2 MHz C64

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               This circuit was developed by Marko Hahn and
           published in the german C64 mag "64'er" issue Feb. 1994
               scanned and translated by Mr.Shine 7/10/1999

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Archive contents:

 2MHz-C64.txt                   this text
 EPROM.PRG                      EPROM data
 images/$00-$01 emulation.tif   circuit diagram for emulation of 6510 $00/$01
 images/6502 to 6510.tif        circuit diagram for emulation of DMA on 6502
 images/clock multiplier.tif    circuit diagram for clock multiplication
 images/DRAM simulation.tif     circuit diagram for simulating DRAM signals
 images/new clock signal.tif    how the resulting clock should look like


Notes:

 I did not build up the circuit myself (yet...)
 
 the circuit was developed for the new C64 board, so if you're using
 a type 1 board, some modification may be necessary where RAM is concerned
 
 The circuit was originally realized as a euro sized (160x100mm) adapter
 board that fits in the original 6510 socket and another (smaller) one that
 fits in the 2 RAM sockets
 
 The EPROM file is a C64 PRG file. To make a standard binary file out of it,
 cut the first two bytes. Also, filling the file up to 8kB with $FF will
 speed up the programming time with most burners.
 
 As some text on the images is still in german, here's some additional
 translation: 
   Prozessor = CPU
   Sockel = socket
   Adaptersockel = adapter socket
   Hauptplatine = main board
   Takt = clock


How the circuit works:

 In the C64, the 6510 shares it's clock with the VIC. Since the VIC
 cannot be clocked with other than 1MHz (e.g. it derives it's video clock
 from the system clock), you will have to use the original clock and multiply
 only the part the CPU uses (phase 1).
 The next part is the processor. The 6510 can only operate at 1MHz, so you'll
 need to use a 2MHz capable 6502 for realisation. The 6502 is missing (1) the
 DMA capability of the 6510 (AEC signal) and (2) the 6 bit I/O port at
 $00/$01. (1) is fully emulated and (2) is only emulated as far as the MMU
 signals are concerned, the tape port has been skipped. Now to the RAM.
 In the C64 (small board), two 4 bit 64k DRAMS are used; the necessary
 refresh signal comes from the VIC. This refresh signal doesn't fit into the
 new timing, so SRAMS are used and the CAS/RAS signal behavior is emulated.


What you need:

 6x  74HC00
 3x  74LS00
 1x  74LS10
 2x  74LS74
 2x  74LS245
 3x  74HC245
 2x  74HC374
 2x  73HC688
 2x  65C256-10
 1x  2764-15
 1x  6502AP (2MHz)

 1x  resistor 100 Ohms
 1x  resistor 33 kOhms
 
 1x  capacitor 100pF
 2x  capacitor 470pF
 4x  capacitor 680pF
 2x  capacitor 1nF
 1x  capacitor 2.2nF
 25x capacitor 100nF (one for each IC)
 
 1x  switch
 
 some sockets


The circuit:

 1. Emulating the AEC signal (circuit: "6502 to 6510.tif")
 
    The 6502 does not feature DMA capability as the 6510 does. This circuit
    emulates the Tri-State function by using three 74HC245.

 2. Emulating the $00/$01 port (circuit: "$00-$01 emulation.tif")

    The 6510 features a 6bit wide I/O port that is used for communicating
    with the tape drive and the MMU. The tape drive support is skipped here
    due to excessive hardware need.
    The address bus is checked for access to $0001. If AEC is high (ie.
    no DMA access) and R/W indicates a write,  the data bus signals D0-D2
    are passed through to the 74LS74 flipflops whose outputs are connected
    to P0-P2. To ensure correct power-on defaults, the set-signals of the
    flipflops are connected to the system reset signal. Ed.: $00 (port
    direction) is ignored, this may affect compatibility (and give us a way
    to detect the circuit by software).

 3. RAM access (circuit: "DRAM simulation.tif")

    The C64 uses DRAMS. They have a multiplexed address bus, ie. by using
    the RAS and CASRAM signals, first the low nibble and then the high
    nibble are transferred to the chip (the signals are controlled by the
    MMU). During the first half of the clock cycle, the CPU may access the
    RAM, and the second one is for the VIC, which also does the refresh.
    So we must make the VIC believe that its DRAMs are present, but give
    the CPU the ability to access the RAM anytime during the first clock
    cycle of the original clock (ie. two of the new cycles). The circuit
    uses 2 SRAMs for the memory and 2 D-flipflops to demultiplex the bus.
    Also, some additional memory management is needed for ROM and I/O access.
    This is where the EPROM is needed.

 4. Multiplying the clock (circuit: "clock multiplier.tif")

    This is the heart of the circuit. See how the new clock should look
    like in "new clock signal.tif". The resulting clock is not what the
    6502 expects, but it works anyway. The signal is needed to look this
    way because the second half of the original clock cycle may not be
    altered since it's needed by the VIC. You might need an oscilloscope
    to adjust the cap values for the multiplier to have the two new clock
    cycles fit exactly into one half of the old. Also make sure you use
    the 74HC00 as indicated, it's timimg is relevant here.
    With the switch, you can always switch back to the original clock.


Building and testing:

 Once you have completed the first 2 steps, you can already test the circuit:
 
  - connect pin 1 to pin 39 of the processor adapter socket
    (this is to supply the 6502 with the original clock at its pin 37)
  - connect STSIG1 to high
  - power on. Your computer must behave normally now
  
 After step 3, you can test again:
 
  - connect the helper signal A (which should come from the multiplier
    circuit later on) to high
  - connect AEC' to low
  - power on. The computer cannot operate this way, but you will be able
    to test whether the RAM simulation behaves like normal DRAMs

 After step 4, you're done!

-END-
